Showing papers on "Wafer published in 1979"

A gas chromatographic air analyzer fabricated on a silicon wafer

Abstract: A miniature gas analysis system has been built based on the principles of gas chromatography (GC). The major components are fabricated in silicon using photolithography and chemical etching techniques, which allows size reductions of nearly three orders of magnitude compared to conventional laboratory instruments. The chromatography system consists of a sample injection valve and a 1.5-m-long separating capillary column, which are fabricated on a substrate silicon wafer. The output thermal conductivity detector is separately batch fabricated and integrably mounted on the substrate wafer. The theory of gas chromatography has been used to optimize the performance of the sensor so that separations of gaseous hydrocarbon mixtures are performed in less than 10 s. The system is expected to find application in the areas of portable ambient air quality monitors, implanted biological experiments, and planetary probes.

Optical lithographic method and apparatus for copying a pattern onto a semiconductor wafer

Abstract: 1. A photolithographic method of copying a pattern onto a semiconductor disk, particularly for the manufacture of integrated circuits, whereby a mask is imaged onto a photosensitive layer of the semiconductor disk by means of an interposed projection lens, characterized in that at least during exposure the space between the semiconductor disk and the boundary face of the projection lens facing the disk remains filled with a transparent liquid.

The Deposition of Silicon Dioxide Films at Reduced Pressure

Abstract: Films of silicon dioxide have been deposited on silicon substrates by decomposing tetraethoxysilane (TEOS) at 700°–750°C in a reduced pressure CVD reactor. The deposition rate is 200–300 A/min. The thickness uniformity is better than ±1% over a deposition zone capable of holding 100 wafers. The step coverage is conformal, the defect density is very low, and the film stress is compressive and low. The refractive index, infrared spectrum, and film density appear normal for deposited silicon dioxide. The addition of phosphorus compounds causes the deposition rate to increase and the thickness uniformity to degrade. Consequently, this reaction is not suitable for depositing phosphorus‐doped films for integrated circuit applications; however, this reaction appears to be a very good process for depositing undoped films of silicon dioxide.

High resolution, steep profile resist patterns

Abstract: High resolution and steep profile patterns have been generated in a 2.6 μm thick organic layer which conforms to the steps on a wafer surface and is planar on its top. This thick organic layer (a photoresist in the present experiments) is covered with an intermediate layer of SiO2 and a top, thin layer of x‐ray or photoresist. After exposure and development of the top resist layer, the intermediate layer is etched by CHF3 reactive ion etching. The thick organic layer is then etched by O2 reactive ion etching. Submicron resolution with essentially vertical walls in the thick organic material was achieved. The technique is also applicable to photo and electron lithography. It reduces the need for thick resist patterns for the lithography step and, at the same time, ensures high resolution combined with good step coverage.

Spin coating process

Abstract: A process for spin coating a substrate such as a semi-conductor wafer uniformly with a coating solution such as a photographic emulsion by rotating the substrate at a first speed while simultaneously applying the coating solution at a radially moving position. Once the substrate has been initially covered, the speed of rotation of the substrate is increased and rotation continues until a uniform coating is obtained.

Method for conducting heat to or from an article being treated under vacuum

Abstract: A method and apparatus are disclosed for providing heat conduction between an article being treated in a vacuum and a support member by providing a gas under pressure of about 0.5 to 2.0 Torr between the article and the support member. The method and apparatus are described for use in a semiconductor wafer ion implantation system wherein the wafer is clamped to the support member which is cooled. A seal can be provided between the wafer and the support member adjacent the periphery of the article.

Fluorine enhanced plasma growth of native layers on silicon

Abstract: The plasma growth rate of native layers, such as oxide and nitride, on silicon is enhanced by the addition of fluorine. An increase in growth rate is obtained, and the oxide growth rates on doped and undoped portions of the silicon substrate are substantially the same. The fluorine is typically added by means of a fluorinated compound, typically CF4, comprising 0.01 to 5 molecular percent of the plasma. Lower substrate temperatures, typically less than 600 degrees C., may be used, resulting in less warpage of the wafer and less diffusion of dopants.

Method of forming solder bump terminals on semiconductor elements

Abstract: An improved method of forming raised input/output (I/O) terminals on the top surfaces of semiconductor elements of a semiconductor wafer. After via openings are formed through the passivation layer of such elements at locations where the I/O terminals are to be formed, which openings provide access to the metalization layers of the elements photolithographic techniques using a layer of heat resistant photoresist which is laminated to the top surface of the wafer are used to form openings through the photoresist layer to provide access to the metalization layers through the vias. A barrier metal layer is deposited on the exposed surfaces of the photoresist, and the metalization layers, and passivation layer of the elements. The barrier metal layer overlying the photoresist and then the photoresist are stripped from the wafer. The same photolithographic techniques using the same heat resistant photoresist material are used to define openings surrounding the barrier metal lining the via openings. A layer of solder is then deposited on the wafer. The solder overlying the photoresist and then the photoresist are stripped from the wafer. The solder is heated until it reflows to form raised I/O terminals of the devices which terminals each will have a substantially spherical exposed surface.

Apparatus for mechanically clamping semiconductor wafer against pliable thermally conductive surface

Abstract: An apparatus for providing active cooling for semiconductor wafers during implantation in an ion implantation chamber includes a housing incorporating a convexly curved platen. The platen has a coating of a pliable thermally conductive material adhered to the surface thereof. A clamping ring is mounted within the housing in slidable relationship with the convexly curved platen so that the travel of the clamping ring ranges between a receiving position wherein the clamping ring and the convexly curved platen define a slot for receiving a semiconductor wafer and a locked position wherein a semiconductor wafer is firmly pressed against the convexly curved platen by the contact of the clamping ring against the semiconductor wafer at its circumferential edge. In the locked position the wafer substantially conforms on its back side to the contour of the convexly curved platen. An active cooling means is provided for transferring thermal energy away from the platen.

Method for manufacturing variable capacitance pressure transducers

Abstract: A method for manufacturing variable capacitance pressure transducers and an intermediate article of manufacture produced in the practice of this method. In the method, a wafer or doped silicon or other semiconductor material has portions of the semiconductor material removed from spaced areas to form a plurality of recesses in the surface of the semiconductor material. The material is doped to enhance its electrical conductivity. A dielectric material has one of its surfaces coated with spaces areas of electrically conductive material. The semiconductor material is attached to the coated surface of the dielectric material such that the surface recesses in the semiconductor material are in alignment with the conductive areas on the dielectric material. This produces a plurality of electrical capacitors suitable for use as pressure transducers. The capacitance of these transducers is varied as a function of changes in one or more fluid pressures acting on the plates of each of the capacitors, one of these plates being the doped semiconductor material and the other being a conductive area on the dielectric material. Fluid pressure between the plates may be established during manufacture. The intermediate article of manufacture produced by this process may then be cut into a plurality of separate pressure transducers.

Plasma etching using improved electrode

Abstract: Radio frequency plasma etching of conductive coatings on semiconductor slices is improved by the use of a curved electrode which is closer to the slice at the center than at the periphery. Preferably, the electrode is in a symmetrical chamber which contains only one slice, and reactant gases are admitted through apertures in the electrode. An r.f. power source is connected between the electrode and a holder for the slice.

Photovoltaic semiconductor devices and methods of making same

Abstract: A solar cell which has high efficiency and which can be fabricated at low cost is described. The cell includes a semiconductor wafer with a front radiation-receiving surface which is entirely open and free of current conducting grids and also includes an array of interconnection paths which carry photocurrent from the front surface through the cell to metal electrodes on the rear surface of the cell.

Method of polishing a semiconductor wafer

Abstract: A semiconductor wafer (31) is placed on a non-porous, flat, substrate (10), with a thin layer of water (21) interposed therebetween. The substrate (10) with the wafer (31) thereon is placed in a polishing machine (40) where a rotating polishing pad (43) polishes the wafer which is permitted to float free and rotate on the thin layer of water (21) during the polishing operation.

Manufacture of thinned substrate imagers

Abstract: The front surface of a semiconductor wafer and the peripheral edge of the back surface of the wafer are protected by either coating them or by placing the wafer in a special fixture. The so protected wafer is then placed in a chemical bath and thinned to the desired thickness over the entire center region of the back surface. Then a sheet of glass which fits into the thin region within the unthinned rim on the back surface is glued to the back surface to provide a laminated structure. Next, the individual imager devices are separated from one another by cutting through the glass and thinned substrate along lines between the devices.

The V-groove multijunction solar cell

Abstract: A new type of silicon photovoltaic converter has been developed called the V-Groove Multijunction (VGMJ) solar cell. The VGMJ solar cell consists of an array of many individual diode elements connected in series to produce a high-voltage low-current output. All the elements of the cell are formed simultaneously from a single silicon wafer by V-groove etching. The results of detailed computer simulations predict a conversion efficiency in excess of 24 percent for this cell when it is operated in sunlight concentrated 100 or more times. The advantages of this cell over other silicon cells include the capability for greater than 20-percent conversion efficiency with only modest bulk carrier lifetimes, a higher open-circuit voltage, a very low series resistance, a simple one-mask fabrication procedure, and excellent environmental protection provided by a glass front surface.

High capacity etching apparatus and method

Abstract: An apparatus for high-throughput sputter etching or reactive sputter etching of wafers comprises a multi-faceted wafer holder centrally disposed within a cylindrical chamber. A source of r-f power is capacitively coupled to the holder and the cylindrical chamber is grounded. By establishing a suitable plasma within the chamber, simultaneous anisotropic etching of, for example, twenty-four 6-inch wafers can be achieved in an apparatus that is approximately the same size as a conventional parallel-plate reactor that has a capacity of only three 6-inch wafers.

Process for cleaving crystalline materials

Abstract: A process for cleaving boules of single crystal materials such as silicon or germanium into thin wafers. The process comprises creating an inward-directed radial stress concentration completely around a boule which intersects its crystallographic plane of minimum bond strength; and subsequently, triggering the cleavage of a thin wafer from the boule via a shock wave applied normal to its crystallographic plane of minimum bond strength.

Air film system for handling semiconductor wafers

Abstract: In an automated fabrication facility, the thin, fragile silicon wafers in which semiconductor circuits are formed must be transported to and from processing stations with a minimum of contact with other solid objects so as to minimize damage, contamination, and consequent lowering of product yield. This task has been undertaken for some time now, in IBM and elsewhere, by systems based on a lubricating film of air as a means for levitating and moving wafers. However, due to inherent motion instabilities and specific control needs, some solid contact is typically involved in effecting prescribed wafer motion. The need for solid contact control is greatly reduced by the air film system described in this paper. It is based on a surface configuration that combines two fluid mechanics phenomena to generate a supporting air film that provides and guides wafer motion. Wafer transportation and positioning are achieved with the air film operating in conjunction with special control device techniques.

Method for qualifying biased burn-in integrated circuits on a wafer level

Abstract: Integrated circuits in dice on a wafer are biased burn-in qualified by providing two sets of conductors connected to each die by fusible elements, biasing the dice using said conductors during the high temperature burn-in, testing the fusible elements, removing the conductors, and testing the circuits.

End-point determination of aluminum reactive ion etching by discharge impedance monitoring

Abstract: In reactive ion etching, it is found that CCl4 discharge impedance is reduced during aluminum etching and changes markedly at the final aluminum interface. This phenomenon was monitored by measuring the target electrode voltage with a 2‐in. aluminium‐coated Si wafer. This measurement is compared with the 261.6‐nm Al–Cl optical emission spectrum and verified with SEM photographs of the etched wafer. As a result the end points detected by these two methods are consistent with each other and discharge impedance monitoring is applicable as an in‐process monitoring method.

High resolution, steep profile, resist patterns

Abstract: High resolution and steep profile patterns have been generated in a 2.6-μm thick organic layer which conforms to the steps on a wafer surface and is planar on its top. This thick organic layer (a photoresist in the present experiments) is covered with an intermediate layer of SiO 2 and a top, thin layer of X-ray or photoresist. After exposure and development of the top resist layer, the intermediate layer is etched by CHF 3 reactive ion etching. The thick organic layer is then etched by O 2 reactive ion etching. Submicron resolution with essentially vertical walls in the thick organic material was achieved. The technique is also applicable to photo- and electron lithography. It reduces the need for thick resist patterns for the lithography step and, at the same time, ensures high resolution combined with good step coverage.

Thin film magnetic recording heads

Abstract: A magnetic read/write transducer head of the type utilizing thin film materials The method of manufacture comprises steps which deposit a thin film magnetic recording head on a selected substrate having dimensions which enable batch manufacture of a thin film magnetic transducer in combination with its supporting slider assembly The substrate of selected material in large wafer form is subjected to a series of thin film deposition, etching and plating operations to form a plurality of thin film magnetic heads thereon Thereafter, the substrate wafer is diced around each thin film magnetic transducer head with subsequent finishing and polishing to requisite shape thereby to yield the complete integrated slider and transducer head assembly

Method using laser irradiation for the production of atomically clean crystalline silicon and germanium surfaces

Abstract: This invention relates to a new method for removing surface impurities from crystalline silicon or germanium articles, such as off-the-shelf p- or n-type wafers to be doped for use as junction devices. The principal contaminants on such wafers are oxygen and carbon. The new method comprises laser-irradiating the contaminated surface in a non-reactive atmosphere, using one or more of Q-switched laser pulses whose parameters are selected to effect melting of the surface without substantial vaporization thereof. In a typical application, a plurality of pulses is used to convert a surface region of an off-the-shelf silicon wafer to an automatically clean region. This can be accomplished in a system at a pressure below 10 -8 Torr, using Q-switched ruby-laser pulses having an energy density in the range of from about 60 to 190 MW/cm 2 .

Production of semiconductor device

Abstract: PURPOSE:To obtain a semiconductor device where a varactor diode and a PIN diode are stable and the junction having a density distribution is steps can be formed. CONSTITUTION:A P layer is formed on a N-type epitaxial wafer by epitaxial growth, and next, a P layer is formed from the P layer surface by thermal diffusion, or a N layer is formed on the P-type epitaxial wafer by epitaxial growth. Next, N layer is formed from the N layer surface by heat diffusion, thereby forming PN junction.

Method of fabricating amorphous memory devices of reduced first fire threshold voltage

Abstract: The first fire voltage of amorphous memory devices are reduced by forming the storage element of two layers, the first being in the crystalline state and the second being the amorphous state. The process deposits a first layer of switchable material and raises the temperature to crystallize the first layer. The wafer is then cooled and the remainder of the switchable material to form the storage element is deposited in an amorphous state.

Semiconductor substrate and a manufacturing method thereof

Abstract: This invention relates to a semiconductor substrate and a method of manufacturing the same. In a semiconductor manufacturing process for a Si single crystal wafer or the like, before the step of mirror polishing, the rear surface of a Si wafer is ground to form a damaged layer having a certain fixed thickness, the Si wafer is subsequently etched by chemical etching if desired, and the rear surface is further formed with an oxide film by thermal oxidation if desired, whereby a semiconductor substrate exhibiting an intense gettering effect is manufactured.

Modeling of low-pressure deposition of SiO 2 by decomposition of TEOS

Abstract: The deposition of SiO 2 from tetraethylorthosilicate (TEOS) in a hot-wall system at low-pressure conditions has been studied. A two-dimensional model has been developed considering a large number of silicon wafers standing perpendicular to the gas flow. This arrangement is preferred in fabrication technology. The model describes the influence of the relevant process parameters on the thickness distribution of deposited oxide across the wafers and from wafer to wafer. The qualitative dependency of calculated profiles on parameter variations agree with experimental results. By choosing suitable parameters oxide layers with thickness deviations as small as 1.6 percent on the wafer and from wafer to wafer have been achieved.

Ion-beam lithography for IC fabrication with submicrometer features

Abstract: We report an entirely new pattern‐replication technique for IC fabrication. It has demonstrated submicrometer (<0.5 μm) resolution and it has the capability of large throughput (wafer‐levels/h). It utilizes high‐energy protons as the exposing radiation through a mask placed in proximity to a wafer covered with resist. We call this new technique ’’ion‐beam lithography’’ (IBL). System parameters and measurements relevant to the use of IBL as a production technology are discussed and SEM micrographs of submicrometer patterns in PMMA are presented. The technique is similar to x‐ray lithography, in that a pattern is produced in a thin resist film after exposing it to radiation through a mask. High‐energy protons have the same advantage as x rays in eliminating wavelength diffraction problems which limit the resolution of photolithography. Also, a gap (∠15–25 μm) is permitted between the mask and wafer. Ions have an advantage over x rays in that penumbral distortion is avoided by using highly collimated ion beams which are available with present state of the art; ions are collimated using conventional ion‐optical techniques, whereas use of a distant ’’point’’ source is the only feasible scheme for collimation of x rays.

Process for fabrication of semiconductors utilizing selectively etchable diffusion sources in combination with melt-flow techniques

Abstract: A process for fabrication of semiconductor devices comprising the steps of depositing over the surface of a semiconductor wafer a first insulating layer containing impurities which are to be diffused into the wafer so as to form source and drain regions, depositing a second insulating and melt-flow layer which is softened or melted at low temperatures, opening contact windows, forming a third insulating layer which also contains impurities to be diffused into the wafer so as to form source drain regions, subjecting the wafer to a heat treatment so as to cause melt-flow and form source and drain regions by the diffusion and removing the third insulating layer. LSI circuits with a high source-drain breakdown voltage may be fabricated at high yields.

Solar cell and fabrication thereof using microwaves

Abstract: Solar cells are fabricated by spraying a dopant coating onto a semiconductor wafer and heating the surface of the wafer using unipolar microwaves. The resultant controlled heating drives dopant atoms from the coating into the wafer to produce a shallow junction at a selectable depth. Advantageously, metallic conductors are predeposited atop the dopant coating and then sintered to the semiconductor by the same unipolar microwave field concurrently with dopant drive-in. Efficient solar cells can be made with this process using polycrystalline silicon, since with unipolar microwave surface heating the grain boundaries do not become so deeply doped as to short circuit the junctions formed in the individual grains. Unipolar microwave heating also may be used to anneal ion implanted semiconductor devices.