Showing papers on "Wafer published in 1982"

Vibrational Study of the Initial Stages of the Oxidation of Si(111) and Si(100) Surfaces

Abstract: Using high-resolution electron energy loss spectroscopy (EELS) the vibrations of Si(111) and Si(100) surfaces in the early stages of oxidation have been investigated. Three different stages of oxidation, the last being the formation of a thin layer of vitreous SiO2 are identified when the surfaces are held at a temperature of 700K during the exposure with molecular oxygen. We show that also the first two stages involve atomic oxygen in bridging positions between silicon atoms. Small exposures at low temperatures (100 K) produce vibrational features of a different, possibly molecular, species. For higher exposures at the same temperature the spectrum again develops the characteristics of atomic oxygen and the molecular species eventually disappears. Exposure at room temperature leads to a mixture of atomic and molecular oxygen for smaller exposures and to purely atomic oxygen for exposures greater than ∼ 102 L. At room temperature even exposures as high as ∼ 1011 L do not produce the spectrum of vitreous SiO2. The same is found for the “natural”, room temperature grown, oxide layer on silicon wafers which we have studied by introducing the sample into the spectrometer through an air-lock. Annealing of the wafer to 700 K produced the characteristic spectrum of vitreous SiO2. The results are discussed in comparison with previous work.

Workpiece holder for polishing operation

Abstract: The workholder includes a carrier to which a flat perforated template is removably secured. An insert is removably mounted in each hole and removably supports a silicon wafer to facilitate polishing the wafer.

Processes for manufacturing insulated-gate semiconductor devices with integral shorts

Abstract: Process for manufacturing insulated-gate semiconductor devices such as MOSFETs being with a semiconductor wafer (such as silicon) including a drain region, a gate insulating layer initially formed uniformly on the surface of the drain region, and a polysilicon conductive gate layer. A two-stage polysilicon etch procedure is disclosed. The initial etch produces relatively narrow channels with substantially vertical sidewalls. Unetched portions of the polysilicon layer are used as masks during a first P type diffusion to form a shorting extension of the device base region and during the forming of a silicon nitride mask layer by a highly directional process, such as ion implantation, which avoids the formation of any nitride layer on the channel sidewalls. In a subsequent lateral etch step, previously unetched portions of the polysilicon gate electrode layer are etched to define insulated polysilicon gate electrode structures. These structures extend upwardly from and are spaced along the principal surface, and are also spaced from the silicon nitride masks. Then, the silicon nitride masks are each used as a combination diffusion and selective oxidation mask to form MOSFET source and base regions and to oxidize the polysilicon gate electrode sidewalls. The silicon nitride mask is removed, and appropriate electrode metallization applied.

Apparatus for projecting a series of images onto dies of a semiconductor wafer.

Abstract: An apparatus for forming on a semiconductor wafer unit magnification images of a reticle pattern. A reticle (20-30) containing an image pattern corresponding to the size of the desired wafer pattern is substantially uniformly illuminated (34-47) to produce an image which passes through a one-to-one stationary projection optical system (50-59) to form an image of the reticle pattern at a predetermined focal plane. A selectively positionable vacuum chuck (79-83, 201, 202, 302, 303) holds the wafer. An alignment system (60-78) steps and orients the chuck to register markings on the individual sides of the wafer with the projected image of corresponding markings on the reticle. A fluid servo system (100-139) acts on the chuck to hold at least a portion of the wafer in the predetermined focal plane of the projection optical system.

Wafer scale integrated circuit

Abstract: Disclosed is a substrate for an array of integrated circuit dice 10' disposed in a regular array on the monolithic wafer substrate 1. Also disposed on the wafer substrate 1 is a network 11' interconnecting various circuits 10', with other integrated circuits, disposed in the array formed on the wafer for data transfer therebetween. Terminals 12' exist in the network 11' for connection of the connections of the network with the various integrated circuits 10'. The networks are connected to a contact pad by one or more connection pads 13', for power and for data entry, and there is provided an auxiliary lead and contact pad for each network for testing each network for operability, also disclosed in the testing method.

Method of thermal treatment of a wafer in an evacuated environment

Abstract: Semiconductor wafers are coated with metallic film by supporting the wafers individually adjacent a ring-shaped sputtering source. A vacuum chamber sputter coating apparatus has a number of work stations therein, at least one of which includes the ring-shaped sputtering source. Also included is a load lock; and an intermittently rotating vertical plate-like wafer carrier therewithin positioned closely adjacent the chamber entrance, and carrying wafers in turn from the load lock to the work stations. The carrier includes apertures each accepting a wafer therewithin in an upright position, with the wafers edgewise resiliently supported by clips. A chamber door is provided with a vacuum chuck to grasp a wafer presented vertically by a blade-like elevator which cooperates with a cassette and conveyor moving the cassette along a horizontal path below the chamber entrance. Closure of the door inserts the wafer into the clips within the carrier and chamber, and the reverse operation extracts a wafer previously coated at a sputtering work station. Both surfaces of the wafer can be accessed by processing equipment, for example, for wafer heating or cooling at some of the work stations. Thermal transfer for wafer heating or cooling is accomplished by introducing a gas at a pressure of approximately 100 to 1000 microns in a region between the wafer and a heating element or heat sink. The gas conducts thermal energy between the wafer and the heating element or heat sink.

Apparatus for thermal treatment of semiconductor wafers by gas conduction incorporating peripheral gas inlet

Abstract: An apparatus for the uniform thermal treatment of semiconductor wafers by gas conduction holds the wafer in place over a gas filled cavity in opposition to a thermal mass maintained at an appropriate temperature. Gas is introduced behind the semiconductor wafer adjacent its periphery to produce a near-constant gas pressure across the backside of the wafer. The constant pressure produces constant thermal conductivity. Consequently, heat conduction is uniform, the temperature of the wafer is uniform and uniform processing is accomplished across the wafer.

Method for fabricating a semiconductor contact and interconnect structure using orientation dependent etching and thermomigration

Abstract: A method for fabricating a semiconductor device and the semiconductor device so fabricated, wherein the method includes the steps of forming a mesa upon one side of a semiconductor surface and then forming a conduction path from the mesa extending through the slice to the opposite side of the semiconductor substrate. Aluminum/silicon alloy droplets are deposited on the first side and form a liquid eutectic which extends to the opposite side by providing a thermal gradient across the slice causing thermomigration of the liquid eutectic. An electrical circuit is then formed on the opposite side and electrically connected to the metal conductor extending through the substrate as formed by the thermomigration of the liquid eutectic. A semiconductor structure is also described that includes an elevated surface upon the first side of a semiconductor substrate and an indentation in the other side, also the combination of two or more such substrates arranged in a stacked configuration. The elevated surface has an electrically conductive layer thereon which is connected to an electrically conductive material extending from the elevated surface to the indentation in the opposite side of the semiconductor substrate. At least one electrical circuit element is located on the opposite side of the semiconductor substrate and electrically connected to said conductive material upon the opposite side of the substrate.

Apparatus for gas-assisted, solid-to-solid thermal transfer with a semiconductor wafer

Abstract: Apparatus and method are provided for effecting gas-assisted, solid-to-solid thermal transfer with a semiconductor wafer. A semiconductor wafer is loaded at its periphery onto a shaped platen. Sufficient contact pressure from the loading is produced between the wafer and the platen so that significant gas pressure may be accommodated against the back side of the wafer without having the wafer bow outwardly or break. Gas under pressure is introduced into the microscopic void region between the platen and the wafer. The gas fills the microscopic voids between the platen and semiconductor wafer. The gas pressure approaches that of the preloading contact pressure without any appreciable increase in the wafer-to-platen spacing. Since the gas pressure is significantly increased without any increase in the wafer-to-platen gap, the thermal resistance is reduced and solid-to-solid thermal transfer with gas assistance produces optimum results.

Methods and apparatus for polishing a semiconductor wafer

Abstract: A semiconductor wafer (31) is placed in a holder (10) and then positioned on a polishing pad (35) in a polishing machine (40). A mechanical force is applied to the holder (10) to cause a predetermined pressure on the wafer (31) therein as the polishing pad (35) is rotated. Simultaneously, water at a pressure slightly higher than the pressure applied to the wafer (31) is injected into the holder to form a water bearing layer between the wafer and the holder that permits free floating rotative motion of the wafer as it is being polished.

Optical projection printing threshold leveling arrangement

Abstract: Semiconductor fabrication using optical projection apparatus is enhanced in an arrangement having means for producing exposures tailored to the patterns on the conventional photo-mask. A predetermined correction photo-mask capable of producing different exposure levels according to the original mask pattern is superimposed with the original mask on the semiconductor wafer by sequential double exposure using an additional mask change and alignment. A better arrangement provides two beams simultaneously illuminating the two masks; the two beams are recombined with a high quality beam splitter arrangement before reaching the imaging lens. The two masks only have to be aligned to each other once. Afterwards, the wafer is exposed regularly. Therefore, an uncorrected image has the lowest threshold for an isolated opening, medium threshold for equal lines and spaces, high threshold for an isolated opaque line. After the correction scheme, all thresholds are made equal. The correction mask is made of grainless dyes of different light transmission or of one semitransparent substance of different thickness, such as thin layers of iron oxide, chromium or silicon. Standard lithographic patterning techniques, such as subtractive etching, lift off or plating are used to fabricate the correction mask.

Semiconductor printing apparatus with multiple independent temperature control

Abstract: A semiconductor printing apparatus eliminates the alignment error caused by any relative deformation between the mask and the wafer due to variations in parameters such as temperature change, and intermediate processing, for example, etching etc. The apparatus is characterized by the provision of a device for cooling or heating respectively and independently plural different sections of at least either of the mask and the wafer.

X-Ray Wafer Probe for Total Dose Testing

Abstract: An x-ray source has been developed for total-dose irradiation testing of semiconductor electronic devices at the wafer stage of fabrication. This Semiconductor X-ray Test Source, as it is designated, was designed to provide an intense, uniform exposure to the device under test. The dose-rate range of 50 to 2×105 rad(Si) per minute allows test flexibility, high throughput, and facilitates standardization with fixed dose-rate sources. Bias to the die being irradiated is applied by the wafer prober; and a collimator mounted on the probe card permits the irradiation of discrete areas of the wafer or individual die. An electronic shutter system permits manual or automatic operation. A silicon detector provides a direct measurement of the dose-rate delivered to the device under test. Good correlation between doses administered by a cobalt-60 source and the test source has been demonstrated. Routine probe testing sequences can be accomplished automatically through a computer interface. Safety features include an enclosure that is both radiation-safe and light-tight; a vital shutter system; interlocks; and a warning light.

Wafer alignment station

Abstract: An automatic wafer alignment station is disclosed for aligning a wafer having flats about its centroid with the flats oriented in a preselected spatial direction. The wafer is held by a vacuum chuck which is operatively connected to a motor driven carriage for controlled movement about an X axis, to a θ actuator carried by the carriage for controlled rotation about the axis of the chuck, and to a Z actuator carried by the carriage for controlled motion about a Z axis. An X capacitive sensor and a Z capacitive sensor are positioned near the wafer. An X processing and Z compensating circuit is responsive to the X and the Z capacitive sensor output signals and provides an electrical signal that has values which exclusively represent the position of the edge of the wafer along the X axis only over a predetermined angular range. Circuit means including an A/D converter and a microprocessor respond to the electrical signal and produce a plurality of corrective signals to the X, Y, and θ actuators for aligning the wafer about its centroid and for orienting the flats of the wafer in a preselected spatial orientation.

New fabrication process for Josephson tunnel junctions with (niobium nitride, niobium) double‐layered electrodes

Abstract: All hard Josephson tunnel junctions, whose base and counter electrodes are composed of double‐layered niobium nitride (NbN) and niobium (Nb) films, have been successfully fabricated by isolating a junction sandwich formed on a whole silicon wafer with a reactive ion etching technique. The reactive ion etching technique has been used for patterning both base and counterelectrodes, and self‐aligning definition of junction areas has been performed. The fabricated junctions show good quality single‐particle tunneling characteristics and excellent uniformity in critical currents.

Silicon MBE apparatus for uniform high-rate deposition on standard format wafers

Abstract: The design and operation of a second generation silicon MBE apparatus are described. A large sample loading interlock permits rapid introduction of standard format 3–4‐in.‐diam silicon and sapphire substrates. Silicon and metallic species are deposited from dual e‐beam evaporation sources at rates of up to 1/3 μm/min. Dopants are introduced by evaporation from conventional Knudsen cells or by simultaneous, low energy ion implantation. Silicon, metal and ionized dopant fluxes are directly sensed and regulated to within ∠1% of preprogrammed values. Rotation of the substrate yields deposition uniformity of ?1% across a 3‐in. wafer. The system includes instrumentation for low and high energy electron diffraction, Auger electron spectroscopy and residual gas analysis.

Automatic liquid dispensing apparatus for spinning surface of uniform thickness

Abstract: An automatic fluid dispensing apparatus for coating to a substantially uniform thickness a rotating surface, such as the surface of a semiconductor wafer, with a viscous liquid, such as a slurry of passivating glass. The wafer rotation rate is related to the radial movement of a dispensing arm to maintain a constant tangential velocity of the wafer at the radial location of the dispensing arm while a bead of the slurry is dispensed at a constant rate proportional to the tangential velocity to provide a spiral beaded coating of constant volume per square. By allowing the bead to heal during or following the dispense cycle, the viscous liquid spreads to a uniform thickness.

Low temperature gettering of Cu, Ag, and Au across a wafer of Si by Al

Abstract: A set of sandwich structures consisting of a noble metal film of Cu, Ag, or Au on one side of a Si wafer (200 μm thick) and an Al film on the other side was annealed at 540 °C for 100 h to study the gettering of these noble metals across the wafer by Al. Rutherford backscattering spectroscopy was used to analyze the amount of these metals in the Al. A very large quantity of Cu(∼1021 atom/cm3) in the Al film was detected after the annealing but neither Ag nor Au could be found in the Al. The solubility of Cu in Si at 540 °C has been calculated to be 1.7×1014 atom/cm3.

Exposure process and system

Abstract: An X ray exposure process and system for transferring a mask pattern onto a wafer with use of X rays, wherein heights on the mask at many points are measured on a light interference band basis by a mask-height measuring device of non-contact measurement type at an X ray exposure position, the mask being mounted on a chamber which is filled with a He gas and or the like to prevent attenuation of an X ray source, heights on the wafer at many points are measured at a wafer-height measuring position different from said exposure position, and according to the measured results, the wafer is finely moved upwardly or downwardly (that is, deformed) individually independently by means of a chuck which sucks and holds the wafer at many points thereon so that, a gap between the mask and wafer is adjusted to a desired level.

Surface Silicon Crystallinity and Anomalous Composition Profiles of Buried SiO 2 and Si 3 N 4 Layers Fabricated by Oxygen and Nitrogen Implantation in Silicon

Abstract: Buried SiO2 and Si3N4 with residual crystalline surface silicon were fabricated by implantation of O+, O2+, N+ and N2+ into single-crystal silicon with 0.6–3.0×1018 atom/cm2 dose at an energy of 70–150 keV/atom. The implanted silicon wafers were annealed at 1150°C to recover the surface silicon crystallinity and to ensure good Si–O and Si–N bonds. After this, high-quality crystalline silicon layers were grown epitaxially on the implanted surface. The surface silicon damage and the buried layer composition profiles were measured reliably by the Rutherford backscattering method together with the channeling technique. In the buried layers, the O/Si ratio did not exceed the stoichiometric ratio of 2.0 for SiO2 even before annealing. However, the N/Si ratio exceeded the stoichiometric ratio of 4/3 for Si3N4.

Performance and Applications of Passivated Ion-Implanted Silicon Detectors

Abstract: Planar process has been applied to the fabrication of nuclear radiation detectors. Combining techniques of oxide passivation, photoengraving and ion implantation any desired detector shape can be made with small tolerances in geometrical and electrical properties. Extremely low reverse currents are obtained (less than 1 nA cm-2/100 ?m at room temperature) and therefore excellent energy resolutions : 10.6 keV for 5.486 MeV alphas, 1.55 keV for 122 keV gamma-rays with 25 mm2 area detectors, 300 ?m thick. The detectors are capable to be backed at 200° C under vacuum. Due to the fact that arrangements of many detectors on one wafer can be made, new possibilities open up, especially for particle localization in high energy physics. Planar versions of 200, 50 and 20 ?m pitch parallel microstrip detectors have been realized. Results obtained using a beam of 10 GeV/c pions are presented. Close mounting of several detectors allows the construction of telescopes used as live target in high energy physics experiments.

Manufacture of semiconductor device

Abstract: PURPOSE:To improve the mounting precision, by fixing a wafer with a wax material during the dicing process for fully cutting it into pellets, fixing them with a resin so as not to disarrange the aligned pellets, separating them from the wax material and mounting directly onto a lead frame. CONSTITUTION:An unprocessed silicon wafer 53 is secured on a base 52 by means of solder 54. The base 52 is carried on a dicing stage 51 and fixed securely by the vacuum suction through a sucking hole 51a. The wafer 53 is cut by forming grooves 53a with a dicing blade 55 rotating at a high speed, whereby the wafer is completely separated into pellets 56. Subsequently, silicon rubber is supplied on the upper faces of these pellets and into the grooves 53a so as to form a silicon rubber layer 57. Fixing rings 58 and 59 are tightened with screws. The solder 54 is heated and molten, and the rings 58 and 59 are lifted up so as to separate the pellets 56 from the solder 54. The pellets are then conveyed over a lead frame 12, and each pellet is put on a conductive bonding agent 13 by a pushing-down jig 60 for conducting the die bonding.

Gas chromatography system and detector and method

Abstract: There is described a gas chromatographic assembly formed on a semiconductor wafer by etching techniques. There is also described an improved thermal detector for use therewith.

Laser annealing of silicon

Abstract: Silicon is one of the most studied and best understood of all materials because of its importance to the integrated circuit industry. The emergence of laser annealing (1,2) in the last ten years has brought about new insight into some of its basic properties and new ways of processing. A quick look at the way integrated circuits are made reveals the reasons for the interest in laser annealing. To make integrated circuits, manufacturers slice very pure crystals of Si into thin wafers. Then they use complex fabrication techniques to produce electrically doped regions close to the surface of the Si and to produce insulating and conducting films that overlay the surface. These doped regions and films can be as thin as a few hundred atomic layers.

High speed plasma etching system

Abstract: This invention relates to a plasma etching system, which includes a lower flange and a spaced upper flange; a chamber wall mounted between the flanges to form a closed etching chamber; a grounded wafer support plate disposed in said chamber for receiving thereon a wafer to be processed; an electrical insulating element interposed between the chamber wall and the support plate; a sintered or sintered-like porous electrode plate mounted in the chamber in spaced relationship with respect to the wafer; said plate having a gas inlet for receiving a supply of etching gas; circuitry for applying an excitation voltage to this plate, and said chamber having a gas outlet leading to a vacuum source.

Wafer-handling tool

Abstract: A special tool designed for picking up and holding circular silicon wafers, the tool incorporating a spring-biased plunger. As the plunger is withdrawn by the spring, a grooved tip at the end of the extended plunger engages one edge of the wafer, driving the opposite edge of the wafer into an arcuate groove on an opposing surface of the body of the tool.

Compensation mechanisms related to boron implantation in GaAs

Abstract: Two different compensation mechanisms are shown to be responsible for the carrier removal observed after boron implantation in n‐type GaAs: (i) Compensation due to complex lattice defects corresponding to implantation damage and which mainly give rise to two narrow bands in the band gap centered at Ec−0.55 eV and Ev+0.70 eV. These defects and the related compensation vanish after annealing for half an hour at temperatures between 350 and 550 °C by exodiffusion. (ii) Compensation due to chemical effects which consists in the formation of complexes between impurities already present in the wafer and the created defects or the boron atoms themselves. These complexes, which are not observed to exodiffuse, are stable at much higher temperatures, up to around 800 °C. It is shown that these complexes do not generate deep levels. Furthermore, it is established that a boron implantation at relatively high dose (1014 at cm−2) followed by an annealing at 860 °C, leads to a depletion of both the electrically active C...

Method of making CMOS by twin-tub process integrated with a vertical bipolar transistor

Abstract: A process for forming high performance npn bipolar transistors in an enhanced CMOS process using only one additional mask level. The bipolar transistor is formed using a low dose blanket implant to form the base in the substrate n-well, then applying arsenic-implanted polysilicon to form the emitter. The emitter formation involves forming a blanket polysilicon layer over the wafer, then using the additional photomask to confine the subsequent arsenic implant to the emitter, n + and polysilicon contact regions, prior to application of aluminum metallization. The arsenic implanted polysilicon technique provides state-of-the-art bipolar processing as well as improved contact characteristics. The combined polysilicon-aluminum metallization improves step coverage, circuit reliability, and reduces the possibility of aluminum diffusion (spiking) through junctions. The n-type contact resistance is improved by virtue of being implanted with arsenic; the p-type contact resistance is controlled by the diffusion from the p + regions which dope the polysilicon during the emitter drive-in cycle.