Showing papers on "Wafer published in 1983"

Production of large‐area single‐crystal wafers of cubic SiC for semiconductor devices

Abstract: A reproducible process is described for growing a thick single-crystal layer of cubic SiC on a single-crystal Si wafer by chemical vapor deposition. A buffer layer, grown in situ, is used between the cubic SiC and the Si substrate to minimize the effect of lattice mismatch. Layers of up to 34 microns thick and several sq cm in area have been grown. Wafers are obtained by chemically removing the Si substrates from the grown layers. Excellent electron channeling patterns produced by these wafers indicate very good crystal quality. Preliminary electrical measurements have yielded electron mobilities up to 380 sq cm/Vs.

Methods of and apparatus for electroplating preselected surface regions of electrical articles

Abstract: An article, such as a semiconductor wafer (31), is selectively electrolytically plated to form metal deposits, such as contacts (26), adjacent to anodes of diode regions within such wafer by mounting the wafer in a plating chamber (36) opposite first and second electrodes (61 and 62), filling the chamber (36) with a metal plating electrolyte (49) and applying alternatingly plating pulses between the wafer (31) and the first electrode (61) and deplating pulses between the wafer (31) and the second electrode (62) The plating pulses are current controlled yielding a predetermined total plating current The deplating pulses are voltage controlled yielding a deplating current which tends to subside in the course of the plating operation The electrolyte in the chamber is agitated by streams of electrolyte pumped at a comparatively high rate toward the wafer (31) to break down surface layers of electrolyte adjacent to the wafer

Removal of coating from periphery of a semiconductor wafer

Abstract: The specification describes techniques for removing the edge bead region from a coated semiconductor wafer by directing a jet of solvent at the wafer periphery while the wafer is spinning. The flow patterns of debris resulting from this removal are controlled to prevent contamination of the chip sites on the wafer.

Modeling and Analysis of Low Pressure CVD Reactors

Abstract: A detailed mathematical model for the hot wall multiple‐disk‐in‐tube LPCVD reactor is developed by using reaction engineering concepts. This model includes the convective and diffusive mass transport in the annular flow region formed by the reactor wall and the edges of the wafers as well as the surface reactions on the reactor wall. In addition, the model describes the coupling of diffusion between and reaction on the wafers. Variations in gas velocities and diffusion fluxes due to net changes in the number of mols in the deposition are also taken into account as are nonisothermal operating conditions. The combined reactor equations are solved by orthogonal collocation. The deposition of polycrystalline Si from is considered as a specific example, and the model is employed in estimation of kinetic rate constants from published reactor measurements. The effects on the growth rates and film thickness uniformity (within each wafer and from wafer to wafer) of variations in flow rates, reactor temperature profiles, and concentration in the feed stream are analyzed. The model predictions show good quantitative agreement with published experimental data from different sources. Finally, recycle of reactor effluent is considered a typical commercial operating conditions, and it is demonstrated that this modification produces higher growth rates and better film uniformity than can be achieved in conventional LPCVD processing.

Wafer-scale laser pantography: Fabrication of n-metal-oxide-semiconductor transistors and small-scale integrated circuits by direct-write laser-induced pyrolytic reactions

Abstract: A complete set of processes sufficient for manufacture of n‐metal‐oxide‐semiconductor (n‐MOS) transistors by a laser‐induced direct‐write process has been demonstrated separately, and integrated to yield functional transistors. Gates and interconnects were fabricated of various combinations of n‐doped and intrinsic polysilicon, tungsten, and tungsten silicide compounds. Both 0.1‐μm and 1‐μm‐thick gate oxides were micromachined with and without etchant gas, and the exposed p‐Si [100] substrate was cleaned and, at times, etched. Diffusion regions were doped by laser‐induced pyrolytic decomposition of phosphine followed by laser annealing. Along with the successful manufacture of working n‐MOS transistors and a set of elementary digital logic gates, this letter reports the successful use of several laser‐induced surface reactions that have not been reported previously.

Stress in polycrystalline and amorphous silicon thin films

Abstract: Stress in polycrystalline and amorphous silicon thin films deposited on oxidized silicon wafers is determined from the lengthening of the undercut edge of a silicon stripe. The technique measures only compressive stresses, has a stress resolution of 108 dyn/cm2, and a spatial resolution on the wafer of 250 μm. Unannealed silicon thin films deposited on oxide are under high compressive stress (1010 dyn/cm2). This stress is reduced below the resolution by annealing at 1100 °C for 20 min in N2, except for the thinnest polycrystalline silicon films studied (230 nm thick).

Damage induced in Si by ion milling or reactive ion etching

Abstract: Surface damage in Si substrates created by Ar‐ion milling or by reactive‐ion etching in CF4, CHF3, Cl2, SiCl4, or SiF4 has been investigated. Metal‐oxide‐semiconductor capacitors were fabricated on the etched Si substrates, and the interface‐state densities were obtained from capacitance‐voltage measurements. Interface states generated by the dry etching processes were strongly dependent on the etching gas and the bias voltage. Carbon‐based gases (CF4, CHF3) induced more interface states than those without carbon. For the carbon‐based gases, Si samples etched in CHF3 showed lower densities of interface states than samples etched in CF4 under the same conditions. Generation lifetime measurements indicated that samples with large densities of interface states also had short lifetimes. Measurements of oxidation‐induced stacking faults caused by dry etching were consistent with both the interface‐state and lifetime measurements. Thermal annealing of the etched wafers was not effective in reducing the surface ...

Wafer/mask alignment system using diffraction gratings

Abstract: An alignment method in which light is diffracted from a mask grating to a wafer grating and back through the mask grating to produce a set of output diffraction orders. The intensity of the zeroth output order is monitored and the mask is translated and rotated within the plane containing the mask to align the mask with the wafer. Alignment occurs when the intensity of the zeroth output order is at an extremum. The distance between the mask and wafer is also adjusted to extremize the intensity of the zeroth output order to make the wafer lie within the focal plane of the exposure optics. The wafer mask is preferrably a holographic phase grating to simplify production of the grating and to eliminate resist related interference. Two dimensional gratings can be used to achieve alignment with only one grating on each wafer.

Semiconductor fabricating apparatus

Abstract: A semiconductor fabricating apparatus is capable of fabricating a high quality semiconductor with utilization of crystal growth, thermal oxidation of CVD membrane growth at low temperature. The semiconductor fabricating apparatus includes a reaction chamber having a gas inlet and a gas outlet, an insulative support means disposed in the reaction chamber for supporting semiconductor wafers thereon, an infrared lamp means for irradiating exposed surfaces of the semiconductor wafers and an ultra-violet lamp means for irradiating the exposed surfaces of the semiconductor wafers overlappingly with the infrared irradiation.

Wafer holding apparatus and method

Abstract: At least three spring-mounted members disposed around the periphery of an aperture in a wafer-mounting plate are arranged to engage and securely hold edge portions of a semiconductor wafer to be processed. When the spring-mounted members are actuated toward the front side of the plate, a wafer can be freely moved into or out of the aperture from the back side of the plate by means of a vacuum chuck that contacts only the back side of the wafer. After a wafer to be held is inserted within the aperture, the actuated members are released. The released members move toward the back side of the plate and thereby engage the edges of the inserted wafer and exert radial holding forces thereon. The back side of a wafer so mounted is adapted to be brought into resilient engagement with a pedestal element in a processing chamber, thereby ensuring good thermal and electrical contact between the wafer and the pedestal element.

Wafer transfer apparatus.

Abstract: In the transfer of semiconductor wafers from storage boats to quartz boats it has been a problem to align the wafers with slots in the receiving quartz boats. To overcome this problem there is provided a wafer support number (42) having vacuum opening (154) which is shiftable between storage boats (12) and quartz boats (14) by transfer arm (32). The relationship between member (42) and arm (32) is such that the wafer can be aligned with slots (132) in quartz boat (14). Sensors including a light source (405) determine alignment between member (42) and slots (132) and then initiate correct alignment of the member (42) to facilitate unimpeded transfer of the wafers.

Surface denuding of silicon wafer

Abstract: A process is disclosed for preparing silicon wafers having a high quality, high lifetime surface layer and a bulk region characterized by a low lifetime and by a high density of precipitated oxygen gettering sites. A wafer having a relatively high concentration of interstitial oxygen is heated in a reducing ambient at a sufficiently high temperature and a sufficiently long time to cause a surface layer to be denuded of oxygen related defects and dislocations. The temperature is then ramped down to a lower temperature and the wafer is maintained at this lower temperature for a sufficient time to allow precipitation of oxygen within the bulk of the wafer.

Vacuum-type article holder and methods of supportively retaining articles

Abstract: A vacuum-type holder (10) for retaining fragile articles such as semiconductor wafers (16) during a manufacturing operation, such as an electrolytic treatment includes a vacuum-operated support (36) at each of the seats (23) which exerts a supporting force against the underside (32) of the wafer (16) which is opposite to and proportional to a vacuum generated holding force which urges the wafer against the seat. The supporting force, consequently, minimizes bending stresses to which the wafer (16) could otherwise be subjected.

Effect of phosphorus doping on stress in silicon and polycrystalline silicon

Abstract: An investigation of the polysilicon stress properties as a function of film thicknesses and phosphorus doping showed that as‐deposited films are moderately compressive, and become less compressive with increasing film thickness. High temperature PBr3 diffusion in silicon produces wafer bending corresponding to a tensile stress in wafer. Following a PBr3 diffusion, polysilicon films, however, become less compressive. Subsequent oxidation introduces an additional compressive stress component of the order of 2−3×109 dyne/cm2 for oxidation temperatures between ∼900−1000 °C. The thermal expansion coefficients were similar for doped and undoped films (α∼2.9 ppm/°C) and slightly less than for 〈100〉 silicon, while the doped films were found to be less stiff than undoped ones but both were less stiff than 〈100〉 silicon. The observed changes in polysilicon stress due to film thickness and phosphorus doping have been interpreted in terms of a grain growth model wherein those factors which lead to enhanced grain grow...

Photovoltaic imaging for large area semiconductors

Abstract: An imaging system for detecting recombination center defects in a semiconductor wafer in which an oxidized wafer is pre-treated by charging the oxide in a corona discharge and then passing the charged wafer below a stationary bifurcated electrode. A focused laser beam is scanned between the arms of the bifurcated electrode and along its length as the wafer is slowly moved transversely to the direction of laser scanning. The signal from the bifurcated electrode is displayed in an imaging system, one axis of which is synchronized to the laser scanning and the other axis is synchronized to the movement of the wafer.

Method and apparatus for deposition of tungsten silicides

Abstract: An apparatus is provided for obtaining very high quality films by chemical vapor deposition in situations where the deposition is mass transport limited. In accordance with the preferred embodiments, there is provided a vacuum housing which is actively cooled to a temperature below which deposition occurs, while at the same time the wafers are being heated to cause deposition at the wafer surfaces. Also provided are mixing chamber systems to ensure that reactant gases are well mixed and distributed evenly over each wafer surface. Mass transport control is further enhanced by providing an exhaust manifold which scavenges reactant gases from locations distributed throughout the system to achieve an even exhaust. Also provided is a method for depositing silicon-rich tungsten silicides using the above apparatus.

Cooled optical window for semiconductor wafer heating

Abstract: A vapor deposition system is provided which uses electromagnetic radiation for heating of a semiconductor wafer. The source of the electromagnetic radiation is typically a lamp having a color temperature corresponding to a wavelength in the range of 0.3 to 0.9 micrometers, and generally for a particular semiconductor to an energy greater than the energy required to cause transitions from the valence band to the conduction band of the semiconductor material used to construct the wafer and more preferably to a color temperature corresponding to an energy substantially at or above the energy required for direct (vertical) transitions from the valence band to the conduction band, thereby providing very high absorption of the incident radiation and very efficient direct heating of the wafer. No substrate is required for conducting heat to the wafer. The radiation is directed by a reflector through a window forming one side of the deposition chamber and impinges directly on the surface of the wafer. Although the windown is typically chosen to be substantially transparent at the frequencies desired for heating the wafer, some absorption does occur, thereby heating the window as well. To maintain optimum control over the deposition process, the window is typically constructed with two spaced-apart plates and water is pumped therethrough to actively control window temperature.

Charged particle beam lithography machine incorporating localized vacuum envelope

Abstract: A charged particle beam lithography machine includes a beam source and beam steering and forming elements within an evacuated column (10). A stage assembly (30) for supporting a semiconductor wafer or mask is positioned in ambient and proximate the exit end of said beam steering and forming elements. A vacuum envelope apparatus (20) is affixed to the exit end of the beam steering and forming elements so that the outer surface or tip (23) of the vacuum envelope apparatus rests in spaced apart, close coupled opposition to the wafer or mask (28) supported on the stage. The vacuum envelope apparatus includes internal structural members (22) which define an internal vacuum processing zone and at least one surrounding intermediate vacuum zone (21). A graded vacuum seal is formed between the tip of the vacuum envelope and the mask or wafer. The seal extends from the internal vacuum processing zone to the external ambient. Lithographic operations are conducted on the mask or wafer as relative motion between the I stage assembly and beam steering and forming elements is accomplished.

Method for automatically identifying semiconductor wafers

Abstract: A technique for automatically identifying a semiconductor wafer (30) having bar code identification indicia (32) on the front surface (31) thereof. Reading of the code is achieved by rotating the wafer about an axis (34) perpendicular to its front surface (31); directing a beam of radiant energy (37) at the code (32) along a predetermined direction relative to the front surface (31); and sensing, while rotating the wafer, the reflected radiant energy (39) within a second predetermined angular direction relative to the front surface. The bar code used herein is preferably a modified or "stretched" bar code 39 formed on the front surface of the wafer, and having an aspect ratio (i.e., dimension of a space/dimension of a bar) ranging from 1 to 4 (FIG. 2).

Process and apparatus for low pressure chemical vapor deposition of refractory metal

Abstract: A process and apparatus for the low pressure, cold wall, chemical vapor deposition of refractory metals, such as tungsten on a silicon wafer. The silicon wafer is introduced into a loading lock wherein the pressure is reduced to subatmospheric pressure. The silicon wafer is transferred to a deposition chamber where it is heated to an elevated temperature. A refractory metal carbonyl vapor is introduced into the deposition chamber and dissociates to deposit a refractory metal on the silicon wafer. The wafer is transferred to an unloading lock where it is allowed to cool and is then removed.

Photoelectrochemical etching of integral lenses on InGaAsP/InP light‐emitting diodes

Abstract: A photoelectrochemical method has been developed for etching integral lenses on light‐emitting diodes (LED’s). An LED wafer is immersed in an electrolyte and biased at a potential at which the etch rate is directly proportional to light intensity. The image of a photomask is projected onto the surface of the wafer to produce a spatial variation of light intensity to etch the desired shape. The method has been used to etch spherical lenses on the n‐InP substrates of InGaAsP/InP LED’s. Extremely smooth surfaces are obtained for etch rates ≲0.5 μm/min. The resulting lensed LED’s gave the theoretically expected improvement in the light coupled into an optical fiber, indicating that the scattering loss of the lenses was very small. The technique is compatible with the standard LED processing and the apparatus required is relatively simple.

Semiconductor wafer transfer apparatus and method

Abstract: An apparatus for transferring wafers between carriers with different wafer spacings and different wafer capacities includes an elevator with two sets of wafer supporting grooves that extend through a carrier to lift wafers from it to a temporary holding region whereat the first and second groups of wafers can be selectively retained by means of first and second movable retainers and first and second retainer blocks. Each wafer supporting groove includes a steeply inclined surface that contacts one point of an edge of a wafer, urging a peripheral portion of the opposite face against a flat opposite vertical wall of the groove. The steeply inclined surface of another wafer supporting groove contacting the same wafer urges a peripheral portion of the opposite wafer face against a flat vertical wall of the second groove. The first and second retainers each contain V-grooves that are aligned with V-grooves of a corresponding one of the retainer blocks to support alternate wafers in the holding region. The retainers and retainer blocks are laterally shiftable to align the V-grooves of either the first retainer or the second retainer with the odd numbered wafer support grooves.

Method and apparatus for plasma etching a substrate

Abstract: A method and apparatus for plasma etching a substrate, such as a semiconductor wafer, utilizing a multipole surface magnetic field confining within an etching chamber an etching plasma of substantially uniform density throughout its volume. The plasma is produced and maintained by subjecting a gas such as CF 4 to an ionizing discharge within the chamber. Only DC power sources are used for the discharge, so that there is virtually no perturbing radio frequency interference produced. The wafer is consequently easily biased relative to the plasma for controlled fine-scale etching. Low gas pressures permitted by the surface magnetic field result in substantially anisotropic etching of the substrate by dense plasma concentrations.

Semiconductor wafer diffusion boat and method

Abstract: A quartz diffusion boat for carrying semiconductor wafers during very high temperature semiconductor manufacturing operations includes first and second quartz rails having first and second sets of wafer supporting grooves, respectively. Each wafer supporting groove of the first set includes a steeply inclined surface that contacts one point of an edge of a first face of a wafer, urging a peripheral portion of the opposite second face of that wafer against an opposite flat vertical wall of that groove. The steeply inclined surface of a corresponding wafer supporting groove of the second set contacting one point of an edge of the second face of the same wafer urges a peripheral portion of the first wafer face against an opposite flat vertical wall of the second groove. The wafers are prevented from tilting away from either flat vertical wall and therefore are held precisely parallel in the wafer supporting grooves. Rattling the wafers during movement of the boat, and resulting production of silicon dust and quartz dust is avoided.

Manufacture of semiconductor device

Abstract: PURPOSE:To reduce the size of a semiconductor element by scribing a notch with a diamond stylus on the second main surface remotely isolated from a function part such as a p-n junction, and pelletizing the element, thereby suppressing the deterioration of the characteristics of the element due to the scribing. CONSTITUTION:A p-n junction 1 is formed in the vicinity of the first main surface 3 of a semiconductor wafer 6. The wafer 6 is mounted with the surface underside on a transparent vinyl sheet 7 with an adhesive substance on the surface. An electrode pattern formed on the first surface 3 through the sheet 7 is observed by a microscope 12, the position of a diamond stylus 8 of a diamond scriber is adjusted to the pattern, and a notch 4 is scribed on the second main surface 9 along the cleavage with the stylus 8 in Fig. A. The sheet 7 and the wafer 6 and covered with a vinyl sheet 10 in Fig. B, a warpage is applied to the wafer 6, thereby cleaving the wafer 6 along the notch 4.

Liquid waxless fixturing of microsize wafers

Abstract: The disclosure teaches an improved manner of firmly holding a thin brittle wafer, such as a 0.01" thick silicon disc 3" in diameter, so as to allow the wafer to be brought into abrading contact with a moving lap wheel. The fixturing provides a pedestal ground flat and a pad of resilient but firm cellular material bonded on the pedestal and ground flat also. The pedestal and pad are each sized only slightly larger than the wafer to be lapped. A guide ring surrounds the pedestal and pad, leaving only a slight clearance gap therebetween, and further projects away from the pad a distance less than the thickness of the wafer as it will be after lapping. A special liquid is applied as a thin uniform film over the face of the pad, and the wafer is biased against the pad face with a uniform force sufficient to squeeze the film to near zero thickness and into the open cells or pores of the pad. By using liquid that is water soluble, is hygroscopic, and has high surface tension, such as carbo wax polyethylene glycol or an equivalent from the glycol or glycerine family, the liquid squeezed into the cells of the pad create an adhesion to the wafer for holding the same firmly in place even after the biasing force is removed. The pad preferably is formed of polyurethane, but could be from the family including cellular urethane, Pellon perforated pad K, some hard styrofoam materials, or even polystyrene to provide the needed characteristics of good porosity, firmness and resiliency.

1.0‐GHz thin‐film bulk acoustic wave resonators on GaAs

Abstract: This letter reports on a new fabrication technique and experimental results obtained on bulk acoustic wave resonators using thin piezoelectric composite films of A1N on GaAs insulating substrates. The fabrication involves only a wafer top side planar processing compatible with integrated circuit technology. Resonators have been made in the frequency range UHF to 1 GHz in order to demonstrate the fabrication technique and evaluate material performance in resonator devices. Both longitudinal and shear wave resonators have been measured with temperature coefficients of −24 and −26.5 ppm/°C, respectively. Shear wave results were obtained from tilted c‐axis films grown in a dc planar magnetron sputtering system.

Method and apparatus for radiation testing of electron devices

Abstract: A test apparatus for electron devices, such as integrated circuits, at the wafer stage of fabrication, wherein a beam of ionizing radiation is directed through an electrical probe card and onto the wafer under test. The probe card and the radiation beam share a common port through which a selected device or group of devices is exposed, but other devices on the wafer are not similarly exposed. A microscope, supported on a frame, is interchangeable with the radiation beam source, sharing the common port, so that a tested device may be observed.