Showing papers on "Wafer published in 1984"

Plasma reactor having slotted manifold

Abstract: A plasma reactor apparatus is disclosed in which plates having channels are used to redistribute gas uniformly over the surface of a wafer being processed in the reactor. Slot means adjacent the plates provide a final baffle to prevent jetstreams in the gas from impinging directly on the wafer.

New infrared detector on a silicon chip

Abstract: We report a single-crystal Si-Ge structure which works as an efficient photodetector in the wavelength region of up to 1.5 µm. The multilevel structure is grown by molecular-beam epitaxy on an n-type 3-in silicon substrate and consists of the following layers: n+silicon (1000 A), n+Ge x Si 1 - x alloy (1800 A, graded in ten steps from x = 0 to x = 1 ), n+germanium (1.25 µm), undoped germanium (2.0 µm), and p+germanium (2500 A). Top three layers form a germanium p-i-n diode, which is removed from the Ge-Si interface by a buffer layer of high conductivity. An advantage of this structure is that its performance is insensitive to material defects in the buffer layers. Moreover, transmission electron microscopy shows that the density of dislocations introduced by lattice mismatch at the Ge-Si interface falls off with the separation from the interface. Our first experimental structures do exhibit the characteristics of a germanium p-i-n diode. The spectral response curves agree with those given in the literature for germanium, both at room and liquid nitrogen temperatures. For the incident light wavelength of 1.45 µm we have measured a quantum efficiency of 41 percent at T = 300 K. we believe that our approach opens an attractive possibility of fabricating complete infrared optoelectronic systems on a silicon chip.

An Etch for Delineation of Defects in Silicon

Abstract: An investigation of the system shows that preferential etching of crystal defects on silicon surfaces is very sensitive to the concentration ratio of to . This leads to development of a new etch consisting of one part by volume of and one part of 49% . This etch can delineate a wide variety of crystal defects with sharp definition. The shape of dislocation etch pits is uniquely determined by the orientation of wafer surfaces and dislocation lines.

Electronic control of an automatic wafer inspection system

Abstract: A system for automatic micro and macro inspection of patterned wafers, including a X-Y stage for supporting and positioning a wafer at a macro inspection station and a micro inspection station, a plurality of cassettes for storing a plurality of patterned wafers before and after inspection, a transfer arm and apparatus for transferring a wafer from the cassettes to a predetermined location on the X-Y stage, apparatus for centering the wafer on the macro inspection station, apparatus for aligning the wafer to obtain a preselected orientation for macro inspection, an optical system for effecting macro inspection of the wafer and storing a unique image thereof, apparatus for moving the wafer from the macro inspection station to the micro inspection station so that the area of the wafer corresponding to the stored unique image is in a micro optical path, autofocus apparatus for automatically focusing the lowest magnification objective lens on the area of the wafer to derive a real time image, a comparitor for comparing the stored unique image to the real time image, apparatus responsive to the comparison of the stored unique image and the real time image and operative to more precisely position the wafer in the micro optical path, apparatus for using areas of the wafer displaced one from the other to obtain more precise alignment of the wafer, apparatus for performing a pre-established micro inspection of selected areas of the wafer and apparatus for returning the wafer to a storage cassette.

Manufacture of semiconductor device

Abstract: PURPOSE:To obtain a semiconductor device characterized by a low cost and improved reliability, by providing a noble metal layer on the surface of a semiconductor substrate through an ohmic contact layer, performing electrolysis of the surface of the noble metal layer in plating liquid including the ions of the same noble metal, reversing the polarity of a voltage, performing electric plating, thereby forming a uniform rear surface of electrode by few processes. CONSTITUTION:A noble metal layer 8 is provided on the surface of a semiconductor substrate 1 through an ohmic contact layer 7. The surface of the noble metal layer undergoes electrolysis by using plating liquid including the ions of the same noble metal as the noble metal 8. Thereafter, the polarity of a voltage is reversed, and electric plating 9 is performed. For example, the Ti-AuSb layer 7 is formed on the rear surface of a wafer. Then, the surface on the side, where an Ag bump 6 is formed, is covered. The wafer is connected to a positive electrode. A platinum plate is connected to a negative electrode. Ag is plated on the rear surface of the semiconductor substrate 1 in the aqueous solution of AgCN. Then, heat treatment is performed in an N2 atmosphere, and the Ag layer 8 is provided through the ohmic contact layer. Then, the wafer is connected to the positive electrode, and the platinum plate is connected to the negaive electrode, and the electrolysis is performed in the aqueous solution of AgCN. Thus the surface of the Ag layer 8 is cleaned. Then the polarity is immediately reversed, and the plating is performed. Thus the Ag layer 9 is obtained.

Etched silicon vibrating sensor

Abstract: The development of a frequency output absolute pressure sensor is described. The sensor element is etched out of single crystal silicon using boron doping to define the shape of the mechanical resonators on one side of a wafer and the diaphragm on the other.

Plasma processor and method for IC fabrication

Abstract: A plasma processor, for dry etching during a fabricating process for an integrated circuit semiconductor device, including a plasma generating region formed in a waveguide into which microwave power is transmitted. An etchant gas is introduced into the plasma generating region and a plasma is generated. The plasma generating region and a reacting region are kept at a specific gas pressure differential by an evacuating device. The radicals (active etching species) react with the underside of a turned wafer placed on a base plate in the reacting region because the gas is blown against the underside of the wafer by the pressure differential. In particular, the wafer is etched by etchant gases floating the wafer by blowing the gases out of holes in the base plate. The floating wafer processing method provides a higher processing rate and better etching uniformity.

Characterization of LPCVD Aluminum for VLSI Processing

Abstract: Aluminum and aluminum alloys are widely used for metallizing devices in VLSI processing. Such films can be deposited by a variety of techniques, which all presently suffer from inadequate step coverage. In this paper, we discuss the properties of aluminum films deposited by a low pressure chemical vapor deposition process using tri‐isobutyl aluminum as a source. Results of this work demonstrate that this process provides conformal step coverage, introduces no surface states, and promises to yield high wafer throughput. Films deposited on oxidized silicon monitors exhibit excellent properties in terms of chemical purity, adhesion, and electrical resistivity. Films deposited on device wafers prove to be compatible with current VLSI processing in terms of patterning, dry etching, and bondability and appear to have no effect on overall device performance. However, drawbacks of LPCVD aluminum appear to be in its structure‐related properties: namely, electromigration resistance and Al‐Si interdiffusion. These problems and potential solutions are addressed.

Phosphorus‐Doped Polycrystalline Silicon via LPCVD I . Process Characterization

Abstract: We have studied the low pressure chemical vapor deposition (LPCVD) process as applied to the preparation of in situ phosphorus‐doped polycrystalline silicon films. Thickness profiling, electron microprobe, and mass spectrometry have been utilized in the characterization of this process. The addition of phosphine as the dopant bearing precursor molecule was found to result in a factor of 25 decay in film growth rates relative to the intrinsic LPCVD process. The physical and chemical characteristics of samples prepared in this manner are shown to be a strong function of local reactor geometry, with growth‐rate variations of a factor of two within a wafer commonly observed. Mass spectrometry data is presented supporting the proposal that phosphine passivates the silicon surface, and the implications of this phenomenon for altering silicon growth kinetics are discussed. A model is presented accounting for the growth‐rate variations observed within individual wafers, as well as for the sensitivity of the phosphine‐doped process to system geometry.

Single wafer plasma etch reactor

Abstract: A high pressure, high etch rate single wafer plasma reactor having a fluid cooled upper electrode including a plurality of small diameter holes or passages therethrough to provide uniform reactive gas distribution over the surface of a wafer to be etched. A fluid cooled lower electrode is spaced from the upper electrode to provide an aspect ratio (wafer diameter: spacing) greater than about 25, and includes an insulating ring at its upper surface. The insulating ring protrudes above the exposed surface of the lower electrode to control the electrode spacing and to provide a plasma confinement region whereby substantially all of the RF power is dissipated by the wafer. A plurality of spaced apart, radially extending passages through the insulating ring provide a means of uniformly exhausting the reactive gas from the plasma confinement region. Affixed to the upper electrode is a first housing which supplies reactive gas and cooling fluid, and a baffle affixed to the first housing intermediate the upper electrode and a gas inlet forms a plenum above the upper electrode and ensures uniform reactive gas distribution thereover. The first housing and upper electrode are contained within a second housing with an insulating housing therebetween. The upper and lower electrodes are electrically isolated from each other and from ground, so that either or both electrodes may be powered.

Thick-film metallization for solar cell applications

Abstract: The use of an integral printing technique for the fabrication of silicon solar cells is attractive due to its throughput rate, materials utilization, and modular, automatable design. The transfer of this technology from single crystal to semicrystalline silicon requires a significant amount of process optimization. Processing parameters found to be critical include the optimum glass frit content in the silver-based inks, the silver ink firing temperature, and the formation of the back-surface field using screen-printed aluminum layers. Open-circuit voltages as high as 617 mV have been achieved using a novel BSF approach on 4-in wafers. Important mechanisms controlling ink contact resistance, ink sheet resistivity, and ohmic contact on and silicon materials are discussed in this paper. The solar cell stability is a function of the glass frit and the firing temperature of the silver-based inks. Finally, a simple economic analysis, based on the IPEG technique, indicates that screen printing is a cost-effective option when the cell manufacturing is done on a large scale.

Wafer level integration technique

Abstract: Wafer level integration is provided by using individually integrated circuits on a wafer substrate and generating an electrically ordered matrix of functional integrated circuits assigned from a random distribution of functional, partially functional, and non-functional circuits. Each circuit is individually tested for functionality and thereafter a conductive grid is formed on said wafer to interconnect all of the circuits on the wafer. Circuits that are tested as being non-functional are isolated prior to formation of the interconnecting grid by eliminating fuses that provide connections between the defective circuit and the conductive grid. Each matrix row includes redundant decoder lines. The redundant decoder lines are programmed to reassign functional circuits from a semiconductor wafer substrate location to a matrix row location in another matrix row having defective circuits. In this way, complete functional matrix rows are formed. Associated input and output lines are assigned in a similar manner to a correct bit position within an input and output byte.

High resolution, high efficiency I.R. LED printing array fabrication method

Abstract: An IR LED array and method of fabrication having a GaAs wafer with one surface metallized to form a common LED contact. Epitaxially formed on this wafer is a GaAs/GaAlAs heterostructure with successive layers of Ga 1-x Al x As-n, GaAs-p, and Ga 1-y Al y As-p on the other surface, followed by an electrical contact layer of GaAs-p+ and an insulating layer of SiO 2 , discrete areas of the contact and insulating layers being removed by etching to form viewing windows for the individual LEDs, and with the area of the contact layer bordering the viewing windows being exposed and metallized to provide individual LED electrical contacts. In a second embodiment, the GaAs-p+ layer is dispensed with and the transparent electrically conducting coating is applied directly on both the insulating layer bordering the Ga 1-y Al y As viewing windows and over the viewing windows. In a third embodiment, and edge emitting LED variant is provided and in a fourth embodiment, various light barrier designs are proposed for preventing optical crosstalk between the individual LEDs.

Composite back-etch/lift-off stencil for proximity effect minimization

Abstract: This composite back-etch/lift-off stencil method avoids the uncontrolled changes in the properties of contacts in small devices caused by the close proximity of the lift-off resist stencil to the contact area during the precleaning, surface preparation and metal deposition processes. This method limits the area of the wafer exposed to back-etching and thus restores the freedom of choice of contact metallurgy. Back-etching is only applied in the areas of the wafer near to the contact holes; lift-off techniques are used for the rest of the integrated circuit.

Ac Surface Photovoltages in Strongly-Inverted Oxidized p-Type Silicon Wafers

Abstract: Surface photovoltages in Si wafers excited with a chopped 559 nm-wavelength photon beam are analysed using a new half-sided junction model. In this model, the wafer surface with the depletion layer is considered to be one half of the p-n junction. Chopping frequency ranges from 2 Hz through 20 kHz. Four 76 mm-diameter p-type Si wafers having resistivities of 260, 92, 17 and 1.0 mΩ m are used after forming 360 nm-thick wet-oxide layer on their front surfaces. In these wafers, photovoltage increases with resistivity. In three high-resistivity wafers with strongly-inverted surfaces, the inversion capacitances and conductances limit the photovoltages at low frequencies. The obtained inversion time-constant is 7 s for the 17 mΩ m wafer.

Breakdown in silicon oxides (II)—correlation with Fe precipitates

Abstract: Thin silicon oxides of metal‐oxide‐semiconductor (MOS) capacitors were studied by transmission electron microscopy. The MOS capacitors were fabricated on silicon wafers which had been intentionally contaminated by Fe+ ion implantation. It was found that Fe precipitates crossing the SiO2/Si interface penetrated into the silicon oxide from the silicon substrate. They reduced the breakdown strength by inducing singularity points in the silicon oxide.

Chemical vapor deposition apparatus

Abstract: A chemical vapor deposition apparatus has a reactor divided into a reaction space and a purging space by a susceptor for supporting a wafer and a loading chamber communicated through a gate with the reactor. Exhaust units are communicated with the reactor and loading chamber, respectively, so that the pressures in the reactor and loading chamber may be reduced. The susceptor has a plurality of recesses to aid placing or scooping the water. Through a transparent wall on the side of the purging space, the susceptor is heated by a lamp unit disposed outside the transparent wall. The loading chamber includes a wafer transport mechanism for charging a wafer into the reactor or discharging a processed wafer from the reactor. An unprocessed wafer is loaded to the loading chamber from a cassette and the processed wafer is unloaded to the cassette. One or a small number of wafers are processed at one time. A uniform film is deposited with a high reproducibility. The processing rate is high and the chemical vapor deposition apparatus is made compact in size.

Self aligning small scale integrated circuit semiconductor chips to form large area arrays

Abstract: Small scale integrated chips are fabricated from a semiconductor wafer and subsequently pretested and formed into large area arrays with self aligning and self locking characteristics due to the axial orientation of the semiconductor wafer and geometries employed for the chips based upon the wafer orientation, whereby the spacing of abutting chip edges in an array may be less than 7 μm. The chips are fabricated from axial wafer, e.g., silicon axial wafer, wherein the chip boundaries are aligned with vertical {111} planes of the crystalline material so that each of the chips formed from the wafer may be defined within parallelogrammatic like geometries defined by these planes and their intersections. The term "parallelogrammatic like geometries" means all geometric shapes capable of being formed with various vertical {111} planes within the crystalline structure of the wafer. Examples of such shapes are parallelograms of various aspect ratios and variations or combinations of planar figures composed of parallelograms. Specific examples of geometries are diamond shaped or chevron shaped configurations.

Reactive-ion etching method

Abstract: A reactive ion etching method utilizing high frequency voltage wherein cathode drop voltage developed in the vicinity of an electrode disposed for impressing a high frequency power is gradually reduced immediately before stopping the impression of high frequency power at the end of ion etching process, thereby reducing the voltage impressed on an insulation layer within a semiconductor wafer below the breakdown voltage of the insulation layer.

Method for gas-assisted, solid-to-solid thermal transfer with a semiconductor wafer

Abstract: Apparatus and method are provided for effecting gas-assisted, solid-to-solid thermal transfer with a semiconductor wafer. A semiconductor wafer is loaded at its periphery onto a shaped platen. Sufficient contact pressure from the loading is produced between the wafer and the platen so that significant gas pressure may be accommodated against the back side of the wafer without having the wafer bow outwardly or break. Gas under pressure is introduced into the microscopic void region between the platen and the wafer. The gas fills the microscopic voids between the platen and semiconductor wafer. The gas pressure approaches that of the preloading contact pressure without any appreciable increase in the wafer-to-platen spacing. Since the gas pressure is significantly increased without any increase in the wafer-to-platen gap, the thermal resistance is reduced and solid-to-solid thermal transfer with gas assistance produces optimum results.

Optical emission spectroscopy end point detection in plasma etching

Abstract: A method for etching a batch of semiconductor wafers to end point using optical emission spectroscopy is described. The method is applicable to any form of dry plasma etching which produces an emission species capable of being monitored. In a preferred embodiment, as well as a first alternative embodiment, a computer simulation is performed using an algorithm describing the concentration of the monitored etch species within the etching chamber as a function of time. The simulation produces a time period for continuing the etching process past a detected time while monitoring the intensity of emission of the etch species. In a second alternative embodiment, this latter time period is calculated using mathematical distributions describing the parameters of the etching process. In all three embodiments, the actual time that end point of an etching process is reached is closely approximated. In this manner, all wafers in a batch of wafers being etched reach end point while at the same time, the amount of over etching is greatly minimized.

Wafer holding apparatus for ion implantation

Abstract: An apparatus is disclosed for the implantation of ions into semiconductor wafers wherein a plurality of storage compartments are connected through valves to a vacuum chamber. A wafer handling device transfers wafers between the storage compartments and a wafer holding device. The wafer holding device positions the wafers in front of an ion beam source. The wafer holding device is a rotatable frustum having a rear end, front end and four trapezoidally shaped sides. Clamps are provided on each side for holding the wafer against the side.

Dry etching apparatus

Abstract: The invention is directed to a dry-etching apparatus used for etching an aluminum wiring film formed on a wafer, and more particularly to a dry-etching apparatus which can remove chlorides deposited on the surface of the wafer during the dry etching thereof, as well as an etching resist film, without having to take the wafer out. This dry-etching apparatus is provided with an etching chamber, a vacuum antechamber attached to the etching chamber by a gate valve, and a post-treatment chamber attached to the vacuum antechamber. The apparatus is so formed that etched wafers removed to the vacuum antechamber can be sent therefrom to the post-treatment chamber, and then the post-treated wafers can be removed to the vacuum antechamber again, and then removed therefrom to the atmosphere.

Two-step anisotropic etching process for patterning a layer without penetrating through an underlying thinner layer

Abstract: Patterning of a relatively thick silicon nitride layer coating a relatively thin silicon dioxide layer which coats a major surface of a silicon wafer is accomplished by reactive ion etching, without penetrating through the silicon dioxide layer to the major surface of the silicon wafer, by means of a two-step reactive ion etching procedure using a patterned masking layer. During the first etching step the silicon nitride layer is not completely penetrated; during the second step the nitride layer but not the silicon dioxide layer is completely penetrated. The gas mixture for the first etching step differs from that of the second etching step in accordance with prescription that the ratio of the etch rate of silicon dioxide to that of silicon nitride during the second step is significantly smaller than such ratio during the first step. Preferred gas mixtures are oxygen and CHF3 in the ratio of about 0.6 to 1.0 for the first etching step and about 9 to 1 for the second etching step. Other systems of layers and wafers can be similarly patterned by means of two-step etching processes using selections of the gas mixtures in accordance with this prescription for the ratios of etch rates.

Adhesive metal sheet for fixing semiconductor wafer

Abstract: PURPOSE: To offer adhesive metal sheet which is able to use also when the size of small piece of element is above 50mm 2 , by a method wherein pressure sensitive adhesive having the nature to be hardened by light irradiation and reticulated three dimensionary, is provided on a sustaining body having light transmission property. CONSTITUTION: As for sustaining bodies having light transmissive property, plastic films such as polyvinyl chloride, polyethylene terephthalate, polyethylene, and polypropylene are enumerated. As for pressure sensitive adhesive which is provided on the sustaining body having light transmission property, pressure sensitive adhesive composition is used, in which lower-molecular weight compound having at least double photo- polymerization carbon-carbon double bond in a molecule, and photo-polymerization staring agent are compounded to a pressure sensitive adhesive of, for instance, rubbery or aclylic type. After wafer is cut, securing wafer to the wafer fixing metal sheet, when pressure sensitive adhesive layer is hardened and reticulated three dimensionary by light irradiation from the supporting body side of adhesive metal sheet, since the adhesivity is almost lost, the adhesive to the small piece of element of the adhesive metal sheet is largely lowered, and the pick up can be easily carried out even if the size of the small piece of element is above 50mm 2 . COPYRIGHT: (C)1985,JPO&Japio

X-ray lithography system

Abstract: An x-ray lithography system is disclosed in which x-rays are generated by directing a high energy laser beam against a metal target to form an x-ray emitting plasma. The x-rays from the plasma are then directed through a mask towards a resist covered wafer to cause a patterned exposure on the wafer resist coating. The mask, the portion of the target which the laser beam strikes and the portion of the wafer to be exposed are all within an evacuated chamber. The laser, prior to entering the chamber, is split into two separate beams, each of which are focused and directed through a window in the side of the chamber towards the same spot on the target. Apparatus, including an air bearing, seal and positioner, is provided to move the target at periodic intervals. Similar apparatus is provided to move the wafer from exposure section to exposure section. The laser beam system includes a face pumped laser beam amplifier and unidirectional beam expanders to allow the maximum energy to be transferred to the laser beam by the amplifier. A series of two or more laser pulses are provided in order to maximize the energy obtained from the laser amplifier. A magnet and a membrane shield are also provided to prevent high energy particles and dust contaminants from the plasma from effecting the lithography process. A materials handling device is provided for moving wafers, targets and masks and an alignment system operating within the evacuated chamber, positions of the wafer with respect to the mask prior to the exposure thereof.

Planarization of dielectric films on integrated circuits

Abstract: A method for planarizing dielectric films between conductive layers on semiconductor wafers is disclosed. Two successive dielectric layers are deposited over a pattern on a wafer and coated with a polymer which has a substantially flat surface. Planarization is obtained when the wafer is plasma etched with the etch rate of the polymer equal to the etch rate of the second dielectric layer. The etch is stopped when all of the polymer has been removed from the wafer. Selectivity in etch rates between the first and second dielectric layers reduces the problems of nonuniformities and the formation of pin holes in the first dielectric layer.

Monolithic Silicon Bolometers

Abstract: A new type of bolometer detector for the millimeter and submillimeter spectral range is described. The bolometer is constructed of silicon using integrated circuit fabrication techniques. Ion implantation is used to give controlled resistance vs temperature properties as well as extremely low 1/f noise contacts. The devices have been tested between 4.2 and 0.3 K. The best electrical NEP measured is 4 x 10 to the -16th W/Hz to the 1/2 at 0.35 K between 1- and 10-Hz modulation frequency. This device had a detecting area of 0.25 sq cm and a time constant of 20 msec at a bath temperature of 0.35 K.