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Showing papers on "Wafer published in 1986"


Patent
19 Dec 1986
TL;DR: In this paper, a single wafer, semiconductor processing reactor is described, which is capable of thermal CVD, plasmaenhanced CVD and plasma assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing.
Abstract: A high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor includes cooperating arrays of interdigitated susceptor and wafer support fingers which collectively remove the wafer from a robot transfer blade and position the wafer with variable, controlled, close parallel spacing between the wafer and the chamber gas inlet manifold, then return the wafer to the blade. A combined RF/gas feed-through device protects against process gas leaks and applies RF energy to the gas inlet manifold without internal breakdown or deposition of the gas. The gas inlet manifold is adapted for providing uniform gas flow over the wafer. Temperature-controlled internal and external manifold surfaces suppress condensation, premature reactions and decomposition and deposition on the external surfaces. The reactor also incorporates a uniform radial pumping gas system which enables uniform reactant gas flow across the wafer and directs purge gas flow downwardly and upwardly toward the periphery of the wafer for sweeping exhaust gases radially away from the wafer to prevent deposition outside the wafer and keep the chamber clean. The reactor provides uniform processing over a wide range of pressures including very high pressures.

685 citations


Journal ArticleDOI
TL;DR: In this paper, a silicon wafer bonding process is described in which only thermally grown oxide is present between wafer pairs, and the wafers are drawn into intimate contact as a result of the gaseous oxygen between them being consumed by oxidation.
Abstract: A silicon wafer bonding process is described in which only thermally grown oxide is present between wafer pairs. Bonding occurs after insertion into an oxidizing ambient. It is proposed the wafers are drawn into intimate contact as a result of the gaseous oxygen between them being consumed by oxidation, thus producing a partial vacuum. The proposed bonding mechanism is polymerization of silanol bonds between wafer pairs. Silicon on insulator (SOI) is produced by etching away all but a few microns of one of the bonded pair. Capacitor measurements show a 27 μs minority‐carrier lifetime and no degradation of the SOI‐insulator interface. In addition, there is negligible charge at the bonding interface making the technique attractive for three‐dimensional as well as planar SOI applications.

613 citations


Journal ArticleDOI
TL;DR: In this article, the authors used curvature and submicron indentation measurements to study the strength of thin aluminum and tungsten thin films on silicon substrates and found that the film strength increased with decreasing thickness.
Abstract: Substrate curvature and submicron indentation measurements have been used recently to study plastic deformation in thin films on substrates. In the present work both of these techniques have been employed to study the strength of aluminum and tungsten thin films on silicon substrates. In the case of aluminum films on silicon substrates, the film strength is found to increase with decreasing thickness. Grain size variations with film thickness do not account for the variations in strength. Wafer curvature measurements give strengths higher than those predicted from hardness measurements suggesting the substrate plays a role in strengthening the film. The observed strengthening effect with decreased thickness may be due to image forces on dislocations in the film due to the elastically stiffer silicon substrate. For sputtered tungsten films, where the substrate is less stiff than the film, the film strength decreases with decreasing film thickness.

318 citations


PatentDOI
TL;DR: In this article, a microwave discharge technique was used to perform direct nitridation of silicon at a relatively low growth temperature of no more than about 500°C in a nitrogen plasma ambient without the presence of hydrogen or a fluorine-containing species.
Abstract: A process utilizing a microwave discharge technique for performing direct nitridation of silicon at a relatively low growth temperature of no more than about 500° C. in a nitrogen plasma ambient without the presence of hydrogen or a fluorine-containing species. Nitrogen is introduced through a quartz tube. A silicon rod connected to a voltage source is placed in the quartz tube and functions as an anodization electrode. The silicon wafer to be treated is connected to a second voltage source and functions as the second electrode of the anodizing circuit. A small DC voltage is applied to the silicon wafer to make the plasma current at the wafer and the silicon rod equal and minimize contamination of the film.

198 citations


Patent
27 Aug 1986
TL;DR: In this paper, a wafer processing apparatus, comprising a Wafer Processing Station, a key input portion for inputting wafer instructions into the processing station, and at least one portion of the portion for accommodating a carrier for carrying the wafer, is disposed at a front side of the apparatus to which the operator faces when actuating the key input component.
Abstract: A wafer processing apparatus, comprising a wafer processing station for processing a wafer, a key input portion for inputting wafer processing instructions into the wafer processing station, and wherein at least one of a portion for accommodating a wafer carrier for carrying the wafer, a mechanism for taking the wafer out of the wafer carrier and putting it back into the wafer carrier, wafer alignment station for aligning the wafer and a wafer observing station for allowing an operator to observe the wafer, is disposed at a front side of the apparatus to which the operator faces when actuating the key input portion.

195 citations


Patent
24 Feb 1986
TL;DR: In this article, a method for producing a film over a topologically non-planar surface of a material which has a sputter etch rate which is higher in a direction parallel to the plane of the wafer than in an opposite direction perpendicular to the surface, is presented.
Abstract: A method for producing a film over a topologically non-planar surface of a material which has a sputter etch rate which is higher in a direction parallel to the plane of the wafer than in a direction perpendicular to the plane of the wafer. Key steps in the process include first, depositing the material by plasma enhanced chemical vapor deposition while simultaneously sputter etching it. Then second, sputter etching the material. Using this two step process, a substantially conformal or sloped film is produced by repeating the steps consecutively until the desired thickness is obtained. The film can then be substantially planarized if desired, by an extended sputter etch to selectively remove material having a sloped surface rather than a flat surface, since the etch rate is higher parallel to the plane of the wafer than perpendicular to the wafer. If a thicker planar surface is desired, additional material can then be deposited by steps of simultaneous plasma chemical vapor deposition and sputter etch, or by consecutive steps of simultaneous plasma deposition and sputter etch followed by sputter etching.

189 citations


Patent
29 Jul 1986
TL;DR: In this article, a chemical-mechanical (chem-mech) method for removing SiO protuberances at the surface of a silicon chip, such protuberance including "bird heads", is described.
Abstract: A chemical-mechanical (chem-mech) method for removing SiO₂ protuberances at the surface of a silicon chip, such protuberances including "bird heads". A thin etch stop layer of Si₃N₄ (29) is deposited onto the wafer surface, which is then chem-mech polished with a SiO₂ water based slurry. The Si₃N₄ acts as a polishing or etch stop barrier layer only on the planar portions of the wafer surface. The portions of the Si₃N₄ layer located on the top and at the sidewalls of the "bird' heads" and the underlying SiO₂ protuberances are removed to provide a substantially planar integrated structure.

156 citations


Journal ArticleDOI
TL;DR: In this article, a new annealing procedure at 1405°C was proposed to produce silicon films of excellent quality, essentially free of oxygen precipitates and with sharp interfaces between the Si and the SiO2.
Abstract: Ion beam synthesis of a buried SiO2 layer is an attractive silicon‐on‐insulator technology for high‐speed complementary metal‐oxide‐semiconductor circuits and radiation hardened devices. We demonstrate here a new annealing procedure at 1405 °C that produces silicon films of excellent quality, essentially free of oxygen precipitates and with sharp interfaces between the Si and the SiO2. Buried oxide layers have been formed in Si (100) wafers by implanting 400 keV molecular oxygen at 500 °C to a dose of 1.8×1018 cm−2. Annealing was performed by radiative heating of the back side of each sample to the melt temperature of silicon, TM=1412 °C, so that the buried oxide structure was at 1405 °C. The temperature control relies entirely on the change in optical properties of silicon upon melting. This ensures, without any external feedback, that the surface exposed to the photon flux will remain at TM.

149 citations


Patent
14 Apr 1986
TL;DR: In this article, a dry processing of a substrate is described, where the substrate is exposed to a gas such as an effluent from a gas plasma, having at least one reactive specie, such as a free radical, the gas having substantially no electrically charged particles present.
Abstract: A method and apparatus for dry processing of a substrate is provided. More particularly, a substrate is exposed to a gas, such as an effluent from a gas plasma, having at least one reactive specie, such as a free radical, the gas having substantially no electrically charged particles present. Simultaneously, the substrate is irradiated with ultraviolet radiation to enhance the reaction rate in a controlled manner. Also provided is a means for irradiating the wafer with infrared radiation to heat the wafer independently of the irradiation with ultraviolet radiation.

145 citations


Journal ArticleDOI
TL;DR: In this paper, X-ray photoelectron spectroscopy and ion scattering spectrograms were used to understand the chemical termination leading to the near ideal electrical passivation of silicon surfaces.
Abstract: X‐ray photoelectron spectroscopy and ion scattering spectroscopy studies of HF‐treated silicon surfaces are described in an effort to understand the chemical termination leading to the near ideal electrical passivation of such surfaces. Results suggest a fluorine surface density of order a monolayer chemically bonded to silicon with a partial oxygen contamination due to exposure of the HF‐treated wafer to air, and a physisorbed hydrocarbon layer on top.

140 citations


Patent
19 Feb 1986
TL;DR: In this article, the vapor phase growth on semiconductor wafers is carried out by an apparatus in which a multiplicity of semiconductor Wafers are held by a holder, and the holder is placed in a heater disposed in a reaction vessel.
Abstract: The vapor phase growth on semiconductor wafers is carried out by an apparatus in which a multiplicity of semiconductor wafers are held by a holder so that the semiconductor wafers lie one over another in a vertical direction, and are rotated together with the holder, the holder is placed in a heater disposed in a reaction vessel, a raw material gas supply nozzle and a raw material gas exhaust nozzle are provided within the heater so that the semiconductor wafers are interposed between the gas supply nozzle and the gas discharge nozzle, and the gas supply nozzle and the gas discharge nozzle have gas supply holes and gas discharge holes, respectively, so that a raw material gas can flow on each semiconductor wafer in horizontal directions. When the temperature of the heater is raised by a heating source to heat the semiconductor wafers, the raw material gas is supplied from the gas supply holes to each semiconductor wafer, and thus a uniform layer is grown on each semiconductor wafer from the raw material gas.

Patent
17 Oct 1986
TL;DR: In this article, a vacuum-tight wafer carrier, which contains numerous wafers in vacuum in a sealed box, is placed into a platform inside a vacuum load lock.
Abstract: A system for performing one semiconductor manufacturing operation or sequence of operations with reduced particulate contamination. A vacuum-tight wafer carrier, which contains numerous wafers in vacuum in a sealed box, is placed into a platform inside a vacuum load lock. The platform contains slots and protruding fingers to provide accurate registration of the position of the wafer carrier. After the load lock is pumped down, the door of the wafer carrier is opened, and a transfer arm removes wafers from the wafer carrier, in any desired order, and transfers them one by one through a port into a processing chamber.

Patent
18 Apr 1986
TL;DR: In this paper, a monolithic accelerometer is fabricated with an integral cantilever beam sensing element which is etched out of a silicon wafer from the back surface, and an integrated circuit is then formed on the front surface and dry etching is used to complete the alignment groove.
Abstract: A monolithic accelerometer is fabricated with an integral cantilever beam sensing element which is etched out of a silicon wafer from the back surface. A thermal silicon oxide is formed on both surfaces of a (100) silicon wafer. Silicon oxide is removed from the back surface in a pattern which defines the sides of the cantilever beam and the sides of an alignment groove. The width and orientation of the openings in the silicon oxide are selected to control the depth of etching when the wafer is subsequently etched with an anisotropic etchant. An integrated circuit is then formed on the front surface and dry etching is used to complete the groove and separate the sides of the beam from the wafer.

Patent
13 Jun 1986
TL;DR: In this paper, the integration of Si MOSFETs and gallium arsenide MESFET on a silicon substrate is described, except for contact openings and final metallization.
Abstract: Monolithic integration of Si MOSFETs and gallium arsenide MESFETs on a silicon substrate is described herein. Except for contact openings and final metallization, the Si MOSFETs are first fabricated on selected areas of a silicon wafer. CVD or sputtering is employed to cover the wafer with successive layers of SiO 2 and Si 3 N 4 to protect the MOSFET structure during gallium arsenide epitaxy and subsequent MESFET processing. Gallium arsenide layers are then grown by MBE or MOCVD or VPE over the entire wafer. The gallium arsenide grown on the bare silicon is single crystal material while that on the nitride is polycrystalline. The polycrystalline gallium arsenide is etched away and MESFETs are fabricated in the single crystal regions by conventional processes. Next, the contact openings for the Si MOSFETs are etched through the Si 3 N 4 /SiO 2 layers and final metallization is performed to complete the MOSFET fabrication. In an alternative embodiment, Si MOSFETs and aluminum gallium arsenide double heterostructure LEDs are formed in a similar manner.

Patent
03 Mar 1986
TL;DR: In this article, an automatic wafer probing system is described inside an environmental box filled with a positive pressure dry inert gas, where a probe card produces probe contact with the chip circuits on the wafer and data taken at desired temperatures.
Abstract: An automatic wafer probing system is disclosed as being located inside an environmental box filled with a positive pressure dry inert gas. The wafer to be probed is mounted on a Thermochuck that has a high thermal contact with the wafer. The chuck can be precisely heated or cooled over the temperature range of -60° C. to +200° C. An atmosphere of dry N 2 gas allows sub 0° C. wafer probing without condensation on the wafer. The box is constructed of metal so as to shield any electromagnetic interferance that could possibly disrupt the testing procedure. A probe card produces probe contact with the chip circuits on the wafer and data taken at desired temperatures. The box includes a window that is in registry with the probe contacts and an externally mounted microscope looks through the window at the probe region. The wafer and window are rendered moisture free by dry N 2 gas. The wafer probing action and the probe testing is under the control of a desktop computer.

Patent
11 Jun 1986
TL;DR: In this paper, the etch stop layer is opened in a pre-determined pattern and etchant is introduced through the opening in the etchant stop layer to produce substantial undercut etching of portions of the undercut layer.
Abstract: Folded cantilever structures and solid state force transducers using same are made by chemical etching of a semiconductive wafer. In the chemical etching process, an etch stop layer is provided on a wafer of semiconductive material. The etch stop layer is opened in a certain pre-determined pattern and etchant is introduced through the opening in the etch stop layer to produce substantial undercut etching of portions of the etch stop layer. The opening is patterned to define a support structure (frame) for the folded cantilever portion which is undercut. The etch is terminated such that one end of the undercut folded cantilever structure is supported from the frame and the other end terminates on a structure such as a mass that is supported from the frame by means of the folded cantilever structure.

Patent
19 May 1986
TL;DR: In this article, a wafer process flow encompasses an arbitray repeated layered structure of heteroepitaxial layers of silicon based films with process control throughout the strata of chemical potential and recombination velocity, suitable for both high performance MOS and bipolar transistors with three dimensional transistor capability.
Abstract: A wafer process flow encompasses an arbitray repeated layered structure of heteroepitaxial layers of silicon based films with process control throughout the strata of chemical potential and recombination velocity, suitable for both high performance MOS and bipolar transistors with three dimensional transistor capability. A non-compensated doping technique preserves crystalline periodicity, as does the component delineation by means of anisotropic etching. The wafer is hermetic by means of the semi-insulation films polyimide, and the elimination of phosphorous doped silicon dioxide. A metallurgy system enables a high level integration.

Patent
24 Sep 1986
TL;DR: In this paper, an apparatus for converting control signals of an electrical or optical nature of any other type or signal which may be converted to a change of temperature of a fixed volume of material trapped in a chamber to flexure of a membrane forming one wall of the chamber.
Abstract: There is disclosed herein an apparatus for converting control signals of an electrical or optical nature of any other type or signal which may be converted to a change of temperature of a fixed volume of material trapped in a chamber to flexure of a membrane forming one wall of the chamber. Typically the device is integrated onto a silicon wafer by anisotropically etching a trench into said wafer far enough that a thin wall of silicon remains as the bottom wall of the trench. In some embodiments, polyimide is used as the material for the membrane. The trench is then hermetically sealed in any one of a number of different ways and the material to be trapped is either encapsulated during the sealing process or later placed in the cavity by use of a fill hole. Typically, a resistor pattern is etched on the face of a pyrex wafer used as a top for the trench to form the cavity. When current is passed through this resistor, the material in the cavity is heated, its vapor pressure increases and expansion occurs. This causes the flexible wall to flex outward. This outward flex movement may then be used to either shut off a fluid flow path, or be sensed in some manner when using the device as a transducer. Typically, a fluid passageway having a nozzle aperture surrounded by a sealing surface is photolithographically etched into a third wafer. This third wafer is then bonded to the first wafer such that the sealing surface is adjacent to the membrane such that when expansion in the cavity occurs, the membrane flexes until it contacts the sealing surface and shuts off fluid flow through the nozzle aperture.

Patent
28 Apr 1986
TL;DR: In this paper, a sputter machine is provided in which the supporting mechanism can be isolated from the sputtering source, the pumps and other processing apparatus for cleaning without exposing the entire machine to atmosphere.
Abstract: A machine for sputter deposition of a wafer workpiece also sputters on the wafer supporting mechanism. This causes a need for cleaning or replacement of the support mechanism. A sputter machine is provided in which the supporting mechanism can be isolated from the sputtering source, the pumps and other processing apparatus for cleaning without exposing the entire machine to atmosphere.

Patent
04 Dec 1986
TL;DR: In this article, a layer of a substance such as an aluminum alloy is deposited, preferably by sputtering, onto a surface of a substrate such as a semiconductor wafer, and the deposited substance is redistributed by bombarding the layer with ions.
Abstract: A layer of a substance such as an aluminum alloy is deposited, preferably by sputtering, onto a surface of a substrate such as a semiconductor wafer. The deposited substance is redistributed by bombarding the layer with ions. The ion bombardment may be induced by applying low frequency RF excitation at about 5 KHz -1 MHz to the substrate.

Journal ArticleDOI
TL;DR: In this paper, a low temperature epitaxial silicon process with UHV/CVD is described, and the transition to high quality, low defect density material to occur between 750° and 800°C, and such films were found to be of high chemical purity.
Abstract: Fundamental equilibrium considerations derived from the system have been successfully employed in the design and operation of a novel low temperature epitaxial silicon process. Films have been deposited in the range, with all resulting material epitaxial. TEM studies showed the transition to high quality, low defect density material to occur between 750° and 800°C, and such films were found to be of high chemical purity as well. In addition, UHV/CVD is shown to be a high throughput multiwafer system, achieving good film uniformities in a high wafer packing density environment, attributable to operation in the low pressure limit of chemical kinetics.

Patent
Mati Mikkor1
30 Oct 1986
TL;DR: In this article, two highly-doped electrically semiconductive feedthrough paths are formed through one wafer, each path contacting one of the capacitive plates, and a glass layer is formed on one of them where bonding is desired between the two wafers.
Abstract: A method of bonding two silicon wafers each having a capacitive plate. Two highly-doped electrically semiconductive feedthrough paths are formed through one wafer, each path contacting one of the capacitive plates. A glass layer is formed on one of the silicon wafers where bonding is desired between the two wafers. The glass layer is anodically bonded to the other of the silicon layers.

Patent
07 Apr 1986
TL;DR: An automatic system for sheet resistivity testing on surface layers of semiconductor wafers, including a wafer handling stage having a platform for carrying a semiconductor Wafer, and an arrangement for mounting the platform for rotation about a central axis and for translation of the platform orthogonal to a major surface thereof, is presented in this paper.
Abstract: An automatic system for performing sheet resistivity testing on surface layers of semiconductor wafers, including a wafer handling stage having a platform for carrying a semiconductor wafer, and an arrangement for mounting the platform for rotation about a central axis and for translation of the platform orthogonal to a major surface thereof. A platform drive translates the platform between a wafer test position and a wafer load position, and a stage drive rotates the platform to accurately located angular test positions. A probe handling arrangement includes a carriage for carrying a test probe parallel to the major surface of a wafer on the platform and a carriage drive translates the carriage between a parked position in which a test prove thereon is positioned adjacent and clear of the platform and accurately located test positions along a radius of the platform. The carriage carries a resistivity test probe which includes test probe element for contacting the surface of a semiconductor wafer. A light tight housing surrounds the platform and includes an access door therein facing the platform and positioned intermediate the wafer load position and the wafer test position of the platform. The access door translates under controlled motor drive between a closed position and an open position which permits the platform to translate between the wafer load and wafer test positions. Sensor arrangements cooperate with a safety inhibit circuit to preclude destructive movement of components when position conflict is sensed. All movements and measurements are under microcomputer control.

PatentDOI
TL;DR: In this paper, an apparatus for testing IC chips on a semiconductor wafer is disclosed that allows the wafer and an electrical probe to be independently positioned and then clamped together and moved as a single unit when they are in alignment.

Patent
16 May 1986
TL;DR: In this article, the benefits of single wafer polishing are achieved with the economies of multiple wafer plasming by adding the plurality of floating subcarriers to the conventional carrier.
Abstract: A polishing apparatus has a conventional carrier with a plurality of floating subcarriers. The benefits of single wafer polishing are achieved with the economies of multiple wafer polishing by adding the plurality of floating subcarriers to the conventional carrier. Each subcarrier has a single wafer adhered to its underside. Axial freedom is provided to duplicate the dynamics of single wafer polishing. The required axial freedom is obtained by axially loading each subcarrier via a mechanical spring or via pneumatic/hydraulic devices. In two variations, each subcarrier is also allowed auto-rotational freedom. In another two variations, the subcarriers are rotationally driven. In all variations, the wafers adhered to the floating subcarriers are substantially uniformly polished and the total indicated reading of the maximum deviation on the wafer surface is improved.

Patent
01 Aug 1986
TL;DR: In this paper, the authors propose a process for bonding two wafers together to form a single wafer with a continuous interface, and for selectively burying a low impedance conductor in the wafer, by providing host and guest wafer having substantially the same crystal orientation and periodicity.
Abstract: A process, and product made thereby, for bonding two wafers together to form a single wafer with a continuous interface, and for selectively burying a low impedance conductor in the wafer, by providing host and guest wafers having substantially the same crystal orientation and periodicity. A crystalline boundary n-semimetal is formed on the wafers, which are then brought into intimate contact. If desired, a unipolar conductor is fused to one of said wafers. Then, the wafers are exposed to an elevated temperature, or rapid thermal anneal, in an inert ambient, breaking up any native oxides and diffusing any excess oxygen into the wafer lattices. The guest wafer is then mechanically lapped back and chemically etched. A vertical cascode integrated half H-bridge motor driving circuit made in the guest and host wafers has a source transistor in the host wafer with with the wafer substrate forming the collector of the transistor, an isotype acceptor doped Ge x Si l-x /Si superlattice forming the base, and an overlying a monocrystalline silicon layer forming a compositional emitter, and with an n-semimetal boundary. The sink transistor of the guest is made with the wafer substrate forming the emitter, an isotype acceptor doped Ge x Si l-x /Si superlattice forming the base, and an overlying a monocrystalline silicon layer forming the compositional collector. The guest substrate is terminated with an n-semimetal boundary. A buried conductor contacts the collector of the host transistor and the emitter of the guest transistor.

Patent
17 Apr 1986
TL;DR: In this article, a wafer is introduced into a processing chamber on a transport device and lifting and clamping pins lower and hold the wafer by enlargements on the ends of the clamping pin.
Abstract: A wafer is introduced into a processing chamber on a transport device. Lifting pins receive the wafer from the transport device and lower the wafer to the surface of a chuck. Clamping pins lower and hold the wafer by means of enlargements on the ends of the clamping pins. Grooves on the surface of the chuck and internal channels in the chuck are used to supply gas to the back of the wafer for temperature control.

Patent
15 May 1986
TL;DR: In this paper, an apparatus for planarizing an aluminum layer on a semiconductor wafer includes two deposition sources: the first source applies a refractory metal silicide layer to form a barrier to oxygen.
Abstract: An apparatus for planarizing an aluminum layer on a semiconductor wafer includes two deposition sources. The first source applies a refractory metal silicide layer to form a barrier to oxygen. The wafer is moved to a second deposition source which is an aluminum sputter device including a heater for the wafer, R.F. bias on the wafer and a magnetic mirror behind the wafer to move the plasma away from the wafer.

Journal ArticleDOI
TL;DR: In this paper, a magnetoplumbite type of hexagonal Ba-ferrite films, whose c-axis of crystallites is well oriented perpendicularly to the film plane, have been prepared by means of a conventional rf diode sputtering system.
Abstract: A magnetoplumbite type of hexagonal Ba-ferrite films, whose c-axis of crystallites is well oriented perpendicularly to the film plane, have been prepared by means of a conventional rf diode sputtering system. Morphological and crystallographic characteristics of sputtered Ba-ferrite films depend strongly on preparation conditions such as the distance between target and substrate d T-S and partial pressure of oxygen gas P O2 during the deposition. Ba-ferrite films with smooth surface are prepared at the extended d T-S in the region of low P O2 . Read/write characteristics of Ba-ferrite thin film deposited on thermally oxidized silicon wafer with radius of two inches were evaluated with ring type head. Recording density D 50 of Ba-ferrite thin film rigid disk depends strongly on Δθ 50 . In this work, D 50 of 110 and 190 kfrpi for Δθ 50 of 4.8 and 2.8°, respectively, have been attained.

Patent
Takashi Kato1
13 Jun 1986
TL;DR: A multi-layer semiconductor device comprising of a stacked wafer body consisting of a plurality of sets (4) of two semiconductor wafers and a heat sink plate (3) interposed there between, with an end of the heat skin plate being exposed at at least one of the side surfaces of the stacked Wafer body as discussed by the authors.
Abstract: A multi-layer semiconductor device comprising: a stacked wafer body (7) consisting of a plurality of sets (4) of two semiconductor wafers (1) and a heat sink plate (3) interposed therebetween, an end of the heat sink plate (3) of each set (4) of wafers being exposed at at least one of the side surfaces of the stacked wafer body (7), there being an intermediate connecting circuit (8) provided for connecting circuits in each set of wafers (4), the intermediate connecting circuit (9) being provided on at least one side surface other than the surface at which the ends of the heat skin plates (3) are exposed