Showing papers on "Wafer published in 1987"

Introduction to microelectronic fabrication

Abstract: (NOTE: Each chapter concludes with Summary, References, and Problems) Preface 1 An Overview of Microelectronic Fabrication A Historical Perspective An Overview of Monolithic Fabrication Processes and Structures Metal-Oxide-Semiconductor (MOS) Processes Basic Bipolar Processing Safety 2 Lithography The Photolithographic Process Etching Techniques Photomask Fabrication Exposure Systems Exposure Sources Optical and Electron Microscopy Further Reading 3 Thermal Oxidation of Silicon The Oxidation Process Modeling Oxidation Factors Influencing Oxidation Rate Dopant Redistribution During Oxidation Masking Properties of Silicon Dioxide Technology of Oxidation Oxide Quality Selective Oxidation and Shallow Trench Formation Oxide Thickness Characterization Process Simulation 4 Diffusion The Diffusion Process Mathematical Model for Diffusion The Diffusion Coefficient Successive Diffusions Solid-Solubility Limits Junction Formation and Characterization Sheet Resistance Generation-Depth and Impurity Profile Measurement Diffusion Simulation Diffusion Systems Gettering 5 Ion Implantation Implantation Technology Mathematical Model for Ion Implantation Selective Implantation Junction Depth and Sheet Resistance Channeling, Lattice Damage, and Annealing Shallow Implantation Source Listing 6 Film Deposition Evaporation Sputtering Chemical Vapor Deposition Epitaxy Further Reading 7 Interconnections and Contacts Interconnections in Integrated Circuits Metal Interconnections and Contact Technology Diffused Interconnections Polysilicon Interconnections and Buried Contacts Silicides and Multilayer-Contact Technology The Liftoff Process Multilevel Metallization Copper Interconnects and Damascene Processes Further Reading 8 Packaging and Yield Testing Wafer Thinning and Die Separation Die Attachment Wire Bonding Packages Flip-Chip and Tape-Automated-Bonding Processes Yield Further Reading 9 MOS Process Integration Basic MOS Device Considerations MOS Transistor Layout and Design Rules Complementary MOS (CMOS) Technology Silicon on Insulator 10 Bipolar Process Integration The Junction-Isolated Structure Current Gain Transit Time Basewidth Breakdown Voltages Other Elements in SBC Technology Layout Considerations Advanced Bipolar Structures Other Bipolar Isolation Techniques BICMOS 11 Processes for Microelectromechanical Systems-MEMS Mechanical Properties of Silicon Bulk Micromachining Silicon Etchants Surface Micromachining High-Aspect-Ratio Micromachining: The LIGA Molding Process Silicon Wafer Bonding IC Process Compatibility Answers to Selected Problems Index

High performance integrated circuit packaging structure

Abstract: A high speed, high performance integrated circuit packaging structure that may be used for emulating wafer scale integration structures. The preferred embodiment comprises an interposer having a base substrate having alternating insulation and conductive layers thereon, wherein a plurality of the conductive layers are wiring means which are adapted for maintaining an extremely low noise level in the package. The low noise level and low resistance and capacitance of the wiring means allows a plurality of discrete semiconductor segments to be mounted on and interconnected by the integrated circuit package with a significantly reduced number of drivers and receivers than required by Rent's Rule. Each integrated circuit structure of the present invention emulates a large chip or wafer scale integration structure in performance without having to yield the large chip or wafer, and without redundancy schemes. A plurality of these integrated circuit packaging structures are combined by decals to form a central processing unit of a computer or a portion thereof. In an alternate preferred embodiment, the base substrate of the interposer is made of silicon and any required drivers are formed therein, thus substantially eliminating the need for any drivers on each of the discrete semiconductor segments.

Magnetic field-enhanced plasma etch reactor

Abstract: A magnetic field enhanced single wafer plasma etch reactor is disclosed. The features of the reactor include an electrically-controlled stepped magnetic field for providing high rate uniform etching at high pressures; temperature controlled reactor surfaces including heated anode surfaces (walls and gas manifold) and a cooled wafer supporting cathode; and a unitary wafer exchange mechanism comprising wafer lift pins which extend through the pedestal and a wafer clamp ring. The lift pins and clamp ring are moved vertically by a one-axis lift mechanism to accept the wafer from a cooperating external robot blade, clamp the wafer to the pedestal and return the wafer to the blade. The electrode cooling combines water cooling for the body of the electrode and a thermal conductivity-enhancing gas parallel-bowed interface between the wafer and electrode for keeping the wafer surface cooled despite the high power densities applied to the electrode. A gas feed-through device applies the cooling gas to the RF powered electrode without breakdown of the gas. Protective coatings/layers of materials such as quartz are provided for surfaces such as the clamp ring and gas manifold. The combination of these features provides a wide pressure regime, high etch rate, high throughput single wafer etcher which provides uniformity, directionality and selectivity at high gas pressures, operates cleanly and incorporates in-situ self-cleaning capability.

Thermal/microwave remote plasma multiprocessing reactor and method of use

Abstract: A novel cold wall single wafer rapid thermal/microwave remote plasma multiprocessing reactor comprising a vacuum chamber having means for mounting a wafer in the chamber, means for providing optical flux mounted adjacent one wall facing the back side of the wafer for optical heating of the wafer, and ports for plasma injection such that remote plasma can be generated and pumped into the chamber. Ports are provided for gas injection both through the plasma generating chamber and for non-plasma injection. The plasma and non-plasma ports are connected through separate manifolds to a plurality of gas sources. The comprehensive reactor design is such that several wafer processing steps can be done sequentially in situ, while providing for optimization of each processing step.

Wafer transfer system

Abstract: Wafer transfer apparatus for horizontal transfer of a wafer between a cassette and an input station of a vacuum processing system includes a wafer transfer arm with a primary section linked to a secondary section so as to move a wafer in a straight line to a location and orientation station and then to the input station. The actual location of the wafer center and the angular orientation of the wafer flat are determined, and the wafer is rotated to a desired angular orientation at the location and orientation station. A solar cell is used to sense actual wafer position by sensing the wafer edge as it is rotated. The required correction and rotation are calculated from the solar cell output. As the wafer is transferred to the input station, correcting displacements are added to the movement so that the wafer is accurately positioned at the input station. A strain gauge is used to reliably sense wafer presence or absence on the transfer arm.

Integrated, microminiature electric-to-fluidic valve and pressure/flow regulator

Abstract: There is disclosed herein an apparatus for converting control signals of an electrical or optical nature or any other type of signal which may be converted to a change of temperature of a fixed volume of material trapped in a chamber to flexure of a membrane forming one wall of the chamber. Typically, the device is integrated onto a silicon wafer by anisotropically etching a trench into said wafer for enough that a thin wall of silicon remains as the bottom wall of the trench. In some embodiments, polyimide is used as the material for the membrane. The trench is then hermetically sealed in any one of a number of different ways and the material to be trapped is either encapsulated during the sealing process or later placed in the cavity by use of a fill hole. Typically, a resistor pattern is etched on the face of pyrex wafer used as a top for the trench to form the cavity. When current is passed through this resistor, the material in the cavity is heated, its vapor pressure increases and expansion occurs. There is also disclosed herein a pressure regulator and a flow regulator each of which are integrated on a single die using the valve structure disclosed herein.

Semiconductor wafer array with electrically conductive compliant material

Abstract: A semiconductor wafer array comprising a plurality of wafers of semiconductor material. Each of the wafers is provided with cone-shaped or pyramid-shaped vias. Inserted in each of the vias is a correspondingly shaped wad of electrically conductive compliant material for forming continuous vertical electrical connections between the wafers in the stack. The base of each wad makes connection to a bonding pad on the surface of a lower wafer as well as to the electrically conductive compliant material in the lower wafer.

Contactless technique for semicondutor wafer testing

Abstract: A contactless technique for semiconductor wafer testing comprising: depositing charges on the top surface of an insulator layer over the wafer to create an inverted surface with a depletion region and thereby a field-induced junction therebelow in the wafer, with an accumulated guard ring on the semiconductor surface therearound The technique further includes the step of changing the depth to which the depletion region extends below the inverted semiconductor wafer surface to create a surface potential transient, and the step of measuring a parameter of the resultant surface potential transient This technique may be utilized to make time retention and epi doping concentration measurements It is especially advantageous for reducing the effects of surface leakage on these measurements In a preferred embodiment, corona discharges are used to effect the charge deposition configuration Either corona discharge or photon injection are used to change the depletion region depth

Particle Deposition on Semiconductor Wafers

Abstract: The deposition of aerosol particles on semiconductor wafers in the typical manufacturing environment of the clean room has been calculated using the equations of convective diffusion and sedimentation. The result shows that the deposition velocity decreases with increasing particle size in the diffusion regime and increases with increasing particle size in the sedimentation regime, with a minimum deposition velocity occurring in the vicinity of 0.2 μm. The minimum deposition velocity varies from approximately 0.2 × 10−3 to 0.7 × 10−3 cm/s, depending on the size of the wafer, the airflow velocity, and whether the wafer is freestanding or placed on top of a workbench.

Method for planarization of a semiconductor device prior to metallization

Abstract: A method for planarizing a semiconductor slice prior to its metallization is disclosed. The semiconductor slice is processed so as to form the diffusions and underlying interconnection layers using well known techniques. After the deposition and patterning of the last interconnection layer prior to metallization, a layer of the platinum or another metal is deposited onto the slice. The slice is sintered to form a silicide film on those portions of the interconnection layers and diffusions which were directly exposed to the sputtered platinum. A layer of phosphorous-doped dielectric is then deposited, followed by a layer of undoped oxide. Photoresist or another conformal material is spun on to the slice, resulting in a planar top surface. The slice is exposed to a plasma etch which etches both the photoresist and the undoped oxide, resulting in a top surface of the undoped oxide which is substantially planar. Contact vias are etched through the undoped and doped oxides; the silicide film acts as an etch stop, allowing contacts of differing depths to be etched from the planar top surface of the undoped oxide without etching through any of the polysilicon layers to which contact is to be made. A metal such as tungsten is deposited onto the slice to fill the contact vias, and is planarized in the same fashion as was the undoped oxide. The metallization is then sputtered onto the planar surface presented by the planarized undoped oxide and the planarized tungsten, and is patterned and etched to form the desired interconnection pattern.

Counterbalanced polishing apparatus

Abstract: Improved polishing apparatus. The apparatus includes a polishing head which holds a semiconductor wafer against a polishing surface. The apparatus permits the accurate application in small increments of pressure to the semiconductor wafer and provides a polishing head which "floats" and quickly reacts to and compensates for minor variations in the contour of the polishing surface contacting the semiconductor wafer.

Wafer holding mechanism

Abstract: A wafer holding mechanism horizontally holds, one at a time, wafers which are sequentially transported thereto. Wafers are treated with liquids such as an etchant, rinsing liquid, and the like, at the same time that the wafer is rotated at a high speed. The mechanism includes a hollow rotary shaft having an upper end thrust into a housing, a rotary plate horizontally mounted on the upper end of the rotary shaft, chuck pieces provided on the rotary plate for holding an outer peripheral edge of the wafer, the chuck pieces being movable in the radial direction of the rotating plate between a holding position wherein the wafer is tightly held by the chuck pieces and a release position wherein the wafer is free to be removed from the chuck pieces.

Method and apparatus for surface treating of substrates

Abstract: A method for surface treating of thin substrates such as semiconductor wafers, wherein a semiconductor wafer formed with deep and minute trenches on its surface is horizontally placed on a spinner in a chamber with its trenched surface directed up, and then ultraviolet light is emitted to the surface of the wafer to dissolve impurities sticking in the trenches, and thereafter etchant is spouted from a nozzle to the trenched surface of the wafer being spinned about a vertical axis at a high speed, and next the inside of the chamber is rendered at a lower pressure than atmospheric pressure and the atmospheric pressure is recovered after the lapse of a predetermined time, and thus a series of these steps of etchant supplying, pressure reducing, and pressure recovering are carried out until the complete entrance of the etchant into the interior surfaces of the trenches is effected, so as to even or smooth the interior surfaces, and finally the wafer is treated with rinsing, and heating and drying.

Integrated circuit processing system

Abstract: A vacuum-tight wafer carrier, and a load lock suitable for use with this wafer carrier. The wafers are supported at each side by a slightly sloping shelf, so that minimal contact (line contact) is made between the wafer surface and the surface of the shelf. This reduces generation of particulates by abrasion of the surface of the wafer. The carrier also contains elastic elements to restrain the wafers from rattling around, which further reduces the internal generation of particulates. When the wafer carrier is placed into the load lock, its body is lowered from beneath its cover through an aperture into a lower chamber, where wafers are loaded and unloaded under vacuum; the carrier cover remains covering the aperture into the lower chamber, so that the wafers never see any surface which is directly exposed to atmosphere. A wafer transport arm mechanism permits interchange of wafers among one or more processing stations and one or more load locks of this type.

Low‐pressure deposition of high‐quality SiO2 films by pyrolysis of tetraethylorthosilicate

Abstract: The deposition of SiO2 by pyrolysis of tetraethylorthosilicate (TEOS) at pressures below 1 Torr was investigated at temperatures between 650 and 800 °C. We found oxide thickness variations of <±5% for suitable process conditions (PD ≤500 mTorr, wafer spacing ≥4.7 mm, TD <730 °C, deposition rate 16 nm min−1). Tests with 150‐mm wafers showed that uniformities of ±2% can be achieved if the wafer spacing is increased to 10 mm. Raising the deposition pressure improves the step coverage in deep trenches but degrades the thickness uniformity across the wafer. The investigations of etch rates in different media show strong dependences on the anneal temperature for etchants containing HF but only a slight dependence for plasma etching. The dielectric breakdown strength of the oxides was 8 MV cm−1 and the failure rate after 500‐ms current stress at 1 mA cm−2 lower than 20%. We found values for the interface state density of 1×1010 eV−1 cm−2 and for the oxide charge density in the range 3×1010 cm−2 to 2.5×1011 cm−2,...

Manufacture of semiconductor device

Abstract: PURPOSE:To prevent the damage to a gate insulating film by removing a resist film by dry etching, in the condition that a not patterned first insulating film is covered with a conductive layer CONSTITUTION:The surface of an Si wafer 1 is coated with an oxide film 2, and thereon a polysilicon layer 3 is made Then, by CVD method, the obverse and the reverse of the polysilicon layer 3 overlaid on the Si wafer 1 are covered with a nitride film 7 And a resist film 4 is made in the specified region on the nitride film 7 above the surface of the Si wafer 1 Next, with the resist film 4 as a mask, the nitride film 7 is dryetched, thus only the nitride films 7 on the gate electrode formation area at the surface of the Si wafer 1 and on the reverse of the Si wafer 1 are left Then, by oxygen plasma, the resist film 4 is all removed from the surface At this time, since the surface of the oxide film 2 being a conductive material is covered with a polysilicon film 3, the plasma damage to the oxide film 2 by oxygen plasma is prevented

Temporal behavior of modulated optical reflectance in silicon

Abstract: We report on the results of a study of the temporal behavior of the laser‐induced modulated optical reflectance from the surfaces of crystalline silicon wafers, epitaxial silicon films, and ion implanted but unannealed silicon wafers. The observed temporal behavior of this signal appears to be associated with the presence and temporal evolution of electronic surface states.

X-ray reduction projection exposure system of reflection type

Abstract: An X-ray exposure apparatus includes a stage (MS) for holding a mask having a pattern for circuit manufacturing, a stage (MF) for holding a wafer to be exposed to the pattern of the mask with X-rays, and a reflection reduction imaging system, disposed between the mask stage and the wafer stage, including reflecting mirror arrangement, containing at least three but not more than five reflecting mirrors (M1,M2,M3) coated with multi-layer films, for receiving X-rays from the mask and directing then to the wafer to expose the wafer to the pattern of the mask with the X-ray in a reduced scale.

Capacitance pressure sensor

Abstract: A capacitive pressure sensor (47, 75, 100, 130, 170, 190) that is fabricated in a batch process affords isolation for the sensing element (12, 102, 134, 183) and leads from the pressure media and provides stress isolation as well. The pressure sensor (47, 75, 100, 130, 170, 190) is made up of a sandwich construction including a silicon wafer (10) which is etched from one side to make cavities (14) in a plurality of desired locations to form deflecting diaphragms (12, 102, 134, 183), one surface of which acts as a capacitor plate. A glass layer (20) is metallized on both sides and has holes drilled in locations that align with the diaphragms formed on the silicon wafer (10). The glass layer (20) is anodically bonded to the wafer to form capacitance gap of a few microns relative to the one surface of each diaphragm (12, 102, 134, 183). The assembly of the metallized glass layer (20) and the silicon wafer (10) is in a preferred form sandwiched between two additional layers (30, 42, 154, 161, 163), and bonded together in a vacuum atmosphere. The four layer sandwich is then cut up into individual sensors (47, 75, 100, 130, 170, 190). The initial assembly can be formed to provide dampening of the diaphragm response times and to minimize the likelihood of false signals at high frequency inputs.

A technology for high-performance single-crystal silicon-on-insulator transistors

Abstract: A process for forming transistors and circuits in a thin single-crystal silicon film on a glass substrate is presented. The process involves the electrostatic bonding of a silicon wafer to glass and the subsequent thinning of the wafer using doping-sensitive etchants to retain only the epitaxial layer. NMOS transistors have shown channel mobilities of 640 cm2/V-s, while leakage currents have been measured at less than 10-14A/µm.

Low Pressure CVD of Silicon Nitride

Abstract: A model of the hot wall tubular reactor for low pressure chemical vapor deposition (LPCVD) is applied to the study of silicon nitride film growth from dichlorosilane and ammonia. The model predicts the effects of process conditions and reactor configuration on distributed wafer growth rate profiles. The model formulation includes contributions from convection, multicomponent diffusion, and gas and surface reactions of several chemical species. Rival chemical mechanisms are compared to experimental data obtained in a conventional LPCVD reactor over widely varying conditions. Results indicate that the in‐wafer film thickness nonuniformities may be explained by the effect of diffusion‐limited film growth from highly reactive gas‐phase intermediates, with simultaneous uniform deposition from less reactive dichlorosilane. Model predictions agree well with experimental data over the composition, pressure, and temperature ranges considered. The model is also used in the design of optimal operating conditions for 100 and 150 mm wafer processes.

Method for producing via holes in polymer dielectrics

Abstract: A method for producing a hole in a polymer film includes the steps of depositing a conductive layer onto the polymer film and irradiating a spot on the layer with a burst of focused laser energy at a level sufficient to form an opening in the film and, subsequently, plasma etching the film so as to form a hole of desired depth in the polymer film underlying the opening in the conductive layer. This method is particularly applicable to the formation of multichip intergrated circuit packages in which a plurality of chips formed in a semiconductor wafer are coated with a polymer film covering the chips and the substrates. The holes are provided for the purpose of interconnecting selected chip contact pads via a deposited conductive layer which overlies the film and fills the holes.

Manufacture of semiconductor device

Abstract: PURPOSE:To realize a quality MESFET provided with a source, a gate, and a drain with the gaps between them constant and smaller and provided with a gate electrode enhanced in thickness by a method wherein a trench is provided in the surface of a semiconductor layer and, in the trench, a Schottky junction is formed between a gate electrode buried in the trench and the semiconductor layer for the construction of a MESFET. CONSTITUTION:On the semi-insulating GaAs substrate 11, an N-type layer 12 is epitaxially grown. Onto the entire surface of such a wafer, an AuGe layer and then an ohmic metal layer 13 are attached. Heat treatment is accomplished, which is followed by patterning whereby a 2.5mum gap is provided between a source and a drain. The ohmic metal layer 13 and the N-type layer 12 are then subjected to ion beam etching. A plasma SiO2 film 14 is provided and subjected to etching which is accomplished vertical to the substrate surface. Next, three layers of Ti, Pt, and Au are laid on the entire surface, in that order. Ion beam etching is accomplished at 30 deg. to the direction vertical to the substrate surface, after which Au and Pt are retained only at a gate section 15. Etching follows, after which Ti is retained only under the gate section 15 for the completion of a three-layer Schottky gate electrode.

Manufacture of semiconductor device

Abstract: PURPOSE:To obtain a dynamic RAM whose area per cell is reduced and integration density is increased by separating in the longitudinal direction a diffusion layer of opposite conduction type formed on a substrate surface and a diffusion layer of capacitance part to increase the withstand voltage of this part. CONSTITUTION:A first groove 4 is formed on a P-type single crystal silicon substrate 1 by photoetching. That is, the desired regions of Si3N4 film 3, SiO2 film 2 and silicon substrate 1 are subjected to etching in order, and the groove is formed. A SiO2 film 5 is formed on the whole surface of a wafer and reaction ion etching is applied thereon. The first groove 4 is subjected to the deeper etching to form a second groove 44. Boron is doped on the inner wall of the groove 44, and a P diffusion layer 6 is formed, then a capacitance insulating film 8 is formed. After the vapor growth of polycrystalline silicon 9 is applied on the whole surface of a wafer, the polycrystalline on the surface of the Si3N4 film 3 is eliminated and the polycrystalline silicon 9 is buried in the groove 44. After a contact hole 7 is formed by photoetching, an N diffusion layer 10 is formed on the substrate surface of the contact hole part. At this time, the N diffusion layer 10 and the P diffusion layer 6 are separated by about 0.5-1mum so as to obtain a sufficient withstand voltage.

Dry etching apparatus

Abstract: A dry etching apparatus which includes an anode located at an upper side and a cathode located at a lower side which face each other in a vacuum vessel. A high-frequency power can be applied across the anode and the cathode. A flange section extends from the inner wall of the vacuum vessel, and is located between the anode and the cathode. A semiconductor wafer can be placed on the cathode through a tray. The cathode is moved toward the anode together with the tray and the wafer. When the edge portion of the tray abuts against the flange section, the interior of the vacuum vessel is partitioned into an etching chamber and the other chamber. A magnetic field is applied to the etching chamber from outside the vacuum vessel, and an etching gas is also introduced into the etching chamber. When the etching gas is introduced, the interior of the etching chamber is evacuated to be maintained at a predetermined pressure.

Head slider with an integrated flat magnetic head

Abstract: An integrated structure is provided for magnetic recording which utilizes a silicon wafer having two parallel faces which are crystal planes of orientation 100. One face is designed so as to constitute a displacement plane when used as a read and write device in a magnetic support. The magnetic head has a horizontal structure and is integrated into the silicon wafer in the face having the displacement plane. An electronic circuit is integrated in the silicon wafer in one of the two faces and connections are provided between the magnetic head and the electronic circuit.

Method for etching contact vias in a semiconductor device

Abstract: A method for forming contact vias in order to make electrical connection between conductive interconnection layers is disclosed. The semiconductor slice is processed so as to form the diffusions and underlying interconnection layers using well known techniques. After the deposition and patterning of the last interconnection layer prior to metallization, a layer of platinum or another metal is deposited onto the slice. The slice is sintered to form a silicide film on those portions of the interconnection layers and diffusions which were directly exposed to the sputtered platinum. A layer of phosphorous-doped dielectric is then deposited, followed by a layer of undoped oxide. Photoresist or another conformal material is spun on to the slice, resulting in a planar top surface. The slice is exposed to a plasma etch which etches both the photoresist and the undoped oxide, resulting in a top surface of the undoped oxide which is substantially planar. Contact vias are etched through the undoped and doped oxides; the silicide film acts as an etch stop, allowing contacts of differing depths to be etched from the planar top surface of the undoped oxide without etching through any of the polysilicon layers to which contact is to be made. A metal such as tungsten is deposited onto the slice to fill the contact vias, and is planarized in the same fashion as was the undoped oxide. The metallization is then sputtered onto the planar surface presented by the planarized undoped oxide and the planarized tungsten, and is patterned and etched to form the desired interconnection pattern.

Using a rapid thermal process for manufacturing a wafer bonded soi semiconductor

Abstract: A method of forming a high quality silicon on insulator semiconductor device using wafer bonding. The annealing time for the wafer bonding process is substantially reduced through the use of a rapid thermal annealer, thereby resulting in minimizing the redistribution of the doping concentration resulting from the annealing process.

Single wafer moated process

Abstract: The present invention is directed to the construction of an integrated circuit chip, and to the method of making such a chip from a plate or wafer. In accordance with the present invention a chip is formed to have conductive edge portions disposed on an insulator surface, which portions optionally may further be expanded into a pad. The insulating material electrically isolates the conductive edge portions from the semiconductive body of the chip. The invention may be implemented in redundant fashion to effect a multiplicity of electrical connections to a set of bulk semiconductor integrated circuits formed on the wafer. Each exposed conductive portion on a chip edge and its optional surrounding conductive pad may be reliably surrounded by insulator so that electrical shorts to non-insulating regions are not experienced. By this edge surface structure integrated circuit elements may be stacked in an array, and electrically connected at the edge surfaces thereof, without hazard that any electrical regions of the integrated circuit elements may be contacted, save intentionally through a conductive lead or film connected to the pads.