Showing papers on "Wafer published in 1993"

The Physics of Macropore Formation in Low‐Doped p‐Type Silicon

Abstract: Macropore formation in n‐type silicon is a self‐adjusting phenomenon characterized by a specific current density at the pore tip. At this specific current density, the dissolution reaction changes from the charge‐transfer‐limited to the mass‐transfer‐limited regime. The passivation of the pore walls in hydrofluoric acid is caused by a depletion of holes due to the n‐type doping of the substrate. Equations based on these findings are presented and allow us to precalculate the dimensions of the pores. The validity of the model and its mathematical description is verified in experiments. Pores of a depth up to the wafer thickness and aspect ratios of 250 were etched using this method.

Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits

Abstract: An experimental technique is described for observing the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate. Various approaches to reducing substrate crosstalk (the use of physical separation of analog and digital circuits, guard rings, and a low-inductance substrate bias) are evaluated experimentally for a CMOS technology with a substrate comprising an epitaxial layer grown on a heavily doped bulk wafer. Observations indicate that reducing the inductance in the substrate bias is the most effective. Device simulations are used to show how crosstalk propagates via the heavily doped bulk and to predict the nature of substrate crosstalk in CMOS technologies integrated in uniform, lightly doped bulk substrates, showing that in such cases the substrate noise is highly dependent on layout geometry. A method of including substrate effects in SPICE simulations for circuits fabricated on epitaxial, heavily doped substrates is developed. >

Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits

Abstract: An experimental technique is described for observing the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate Various approaches to reducing substrate crosstalk (the use of physical separation of analog and digital circuits, guard rings, and a low-inductance substrate bias) are evaluated experimentally for a CMOS technology with a substrate comprising an epitaxial layer grown on a heavily doped bulk wafer Observations indicate that reducing the inductance in the substrate bias is the most effective Device simulations are used to show how crosstalk propagates via the heavily doped bulk and to predict the nature of substrate crosstalk in CMOS technologies integrated in uniform, lightly doped bulk substrates, showing that in such cases the substrate noise is highly dependent on layout geometry A method of including substrate effects in SPICE simulations for circuits fabricated on epitaxial, heavily doped substrates is developed >

Micromachined torsional scanner

Abstract: A frequency-locked torsional scanner of the type having a micromachined mirror formed on a surface of a silicon wafer section supported within a larger wafer section by a pair of opposed torsion bars. The principal vibrational frequency of the mirror is selected to be at least 20% higher than other modes of vibration. To prevent breakage, the torsion bars are hardened by conversion of at least a surface layer to silicon carbide or nitride. A pair of scanners with orthogonal torsion bars may be mounted in a vacuum enclosure for two-dimensional scanning at different rates suitable for television display. In alternate embodiments, a detector and a scanner may be built on a plate on the same supported wafer section or two scanners may be independently supported or one scanner and one detector may be independently supported as two plates. The mirror may be driven electrostatically, magnetically, or by both methods.

Susceptor drive and wafer displacement mechanism

Abstract: A thermal reaction chamber for semiconductor wafer processing operations comprising: (i) a susceptor for supporting a semiconductor wafer within the chamber and having a plurality of apertures formed vertically therethrough; (ii) displacer means for displacing the susceptor vertically between at least a first and a second position; (iii) a plurality of wafer support elements, each of which is suspended to be vertically moveable within said apertures and each of which extends beyond the underside of the susceptor; and (iv) means for restricting the downward movement of the wafer support elements. As the susceptor is displaced from its first position through an intermediate position before the second position, the means for restricting operate to stop the continued downward movement of the wafer support elements thereby causing the elements to move vertically upwards with respect to the downwardly moving susceptor and separate the wafer from the susceptor.

Process of manufacturing a three dimensional integrated circuit from stacked SOI wafers using a temporary silicon substrate

Abstract: A method of providing a first and a second Silicon-on-Insulator (SOI) wafer, wherein each SOI wafer includes a silicon layer separated from a bulk silicon substrate by a layer of dielectric material, typically SiO2. Next, at least one electrical feedthrough is formed in each of the silicon layers and active and passive devices are formed in each of the thin silicon layers. Next, interconnects are formed that overlie the silicon layer and are electrically coupled to the feedthrough. One of the wafers is then attached to a temporary substrate such that the interconnects are interposed between the thin silicon layer and the temporary substrate. The bulk silicon substrate of the wafer having the temporary substrate is then etched to expose the dielectric layer. Further interconnects are then formed through the exposed dielectric layer for electrically contacting the at least one feedthrough. This results in the formation of a first circuit assembly. A next step then couples the further interconnects of the circuit assembly to the interconnects of the second SOI wafer, the second SOI wafer having a bulk substrate, a dielectric layer overlying a surface of the substrate, and a layer of processed silicon overlying the dielectric layer. The temporary substrate is then removed. Additional circuit assemblies may then be stacked and interconnected to form a 3d integrated circuit.

System and method for real-time control of semiconductor a wafer polishing, and a polishing head

Abstract: A system for polishing a semiconductor wafer includes a rotatable platen subassembly and a drive mechanism coupled to rotate the platen subassembly at a platen velocity. A polishing head supports and holds a face of the semiconductor wafer in contact with the platen subassembly to polish the wafer face whereby individual regions of the wafer face have different polishing rates. The polishing head includes pressure applicators for applying various localized pressures on the individual regions of the semiconductor wafer to conform the wafer face to a selected contour. The system also includes a polish control subsystem for monitoring in situ the polishing rates at various regions of the semiconductor wafer. The polish control subsystem adjusts in situ the platen velocity and/or the individual localized pressures applied to the semiconductor wafer to change the polishing rates of the individual regions of the semiconductor wafer. The system can also be adapted to change other operational parameters, such as wafer velocity, wafer polishing path across the platen, slurry composition and flow rate (for CMP processes), and force applied to the wafer when contacting the platen. A method for polishing a semiconductor wafer is also described.

Silicon scavenger in an inductively coupled RF plasma reactor

Abstract: A domed plasma reactor chamber uses an antenna driven by RF energy (LF, MF, or VHF) which is inductively coupled inside the reactor dome. The antenna generates a high density, low energy plasma inside the chamber for etching metals, dielectrics and semiconductor materials. Auxiliary RF bias energy applied to the wafer support cathode controls the cathode sheath voltage and controls the ion energy independent of density. Various magnetic and voltage processing enhancement techniques are disclosed, along with etch processes, deposition processes and combined etch/deposition processed. The disclosed invention provides processing of sensitive devices without damage and without microloading, thus providing increased yields.

Plating device for wafer

Abstract: A plating device for a wafer employs an air bag 6, 20 as a holding means for downwardly depressing the wafer 8 upon performing plating on the wafer 8. The air bag 6, 20 constrain only the upper surface 13 of the circumferential edge of the wafer at an expanded state and releases the constraint by contracting to restore an initial configuration at a non-expanded state. By this, the holding means will not occupy the upper side space of the wafer both during plating process and during non-plating process so as to avoid adhering of dust and foreign matter onto the wafer 8.

Method for etching an SiO2 film

Abstract: An NF 3 /H 2 mixture as a feed gas for an etchant for etching an SiO 2 film on an silicon wafer is used with a 1 : 160 NF 3 /H 2 mixed ratio. The mixture is made into plasma, and activated species of fluorine, hydrogen and nitrogen are supplied downstream to allow the species to be adsorbed in and on the SiO 2 film. The NF 3 /H 2 mixed ratio of the mixture is so set as not to effect the etching of the SiO 2 film under a chemical action. Then the adsorbed activated species are irradiated with Ar low energy ions so that the activated species are excited and etch the SiO 2 film. During etching, the semiconductor wafer is maintained to about -100° C. Less damage is caused to the silicon wafer and etching can be made in a high selection ratio.

Apparatus for processing semiconductor wafer comprising continuously rotating wafer table and plural chamber compartments

Abstract: An apparatus for forming a CVD film on semiconductor wafers includes a process chamber in which a rotary table capable of loading five wafers is provided. The interior of the process chamber is divided into six compartments by radially arranged partitions. The compartments comprise a wafer exchanging room for loading and unloading wafers, a first process room for forming a silicon film on the wafers, a second process room for oxidizing the silicon film into silicon oxide film and three exhaust rooms provided between the wafer exchanging room, the first process room and the second process room. The wafers are processed on the continuously rotating table. As the table is rotated, the wafers are processed in the first and second process rooms and unnecessary products produced in them are successively removed in the exhaust rooms.

Apparatus for interlayer planarization of semiconductor material.

Abstract: A pad for planarizing the surface of a semiconductor wafer. The pad includes at least two layers. One layer has a hydrostatic modulus which is different from the hydrostatic modulus of the other pad.

Apparatus and method for real-time measurement of thin film layer thickness and changes thereof

Abstract: A new technique has been developed to measure etching or deposition rate uniformity in situ using a CCD camera which views the wafer during plasma processing. The technique records the temporal modulation of plasma emission or laser illumination reflected from the wafer; this modulation is caused by interferometry as thin films are etched or deposited. The measured etching rates compare very well with those determined by Helium-Neon laser interference. This technique is capable of measuring etching rates across 100-mm or larger wafers. It can resolve etch rate variations across a wafer or within a die. The invention can also be used to make endpoint determinations in etching operations as well as measuring the absolute thickness of thin films.

Manufacture of thin film of semiconductor material

Abstract: PURPOSE: To manufacture a uniform quality and thin semiconductor film by maintaining a wafer temperature during hydrogen or rare-gas ion implantation which is lower than a gas discharge temperature and performing heat processing, while a wafer and a reinforcing material are in close contact with each other. CONSTITUTION: A fine bubble layer 3, which defines a semiconductor wafer 1 as a low region 6 and an upper region 5 constituting a thin film, is caused by implantation to a surface 4 of the wafer 1 by a bombardment 2. Ions are selected from hydrogen gas or rare-gas ions. The wafer temperature during the implantation is maintained to be lower than a temperature for discharging the ion gas from the semiconductor. The flat surface 4 of the wafer 1 is brought into close contact with a reinforcing material 7 of a rigid material layer. By performing heat processing at a temperature of 500 deg.C or higher which is appropriate to separation of the thin film 5 from the bulk of the substrate 6 by a crystal rearrangement in the wafer 1 and pressure in the fine bubbles, and selecting the implantation energy, the thickness of the thin film can be selected within a wide thickness range.

Experimental Investigation of Micro Heat Pipes Fabricated in Silicon Wafers

Abstract: An experimental investigation was conducted to determine the thermal behavior of arrays of micro heat pipes fabricated in silicon wafers. Two types of micro heat pipe arrays were evaluated, one that utilized machined rectangular channels and the other that used an anisotropic etching process to produce triangular channels. Once fabricated, a clear pyrex cover plate was bonded to the top surface of each wafer using an ultraviolet bonding technique to form the micro heat pipe array. These micro heat pipe arrays were then evacuated and charged with a predetermined amount of methanol. Using an infrared thermal imaging unit, the temperature gradients and maximum localized temperatures were measured and an effective thermal conductivity was computed. The experimental results were compared with those obtained for a plain silicon wafer

Damage‐free selective etching of Si native oxides using NH3/NF3 and SF6/H2O down‐flow etching

Abstract: Damage‐free selective etching of Si native oxides against Si has been achieved by NH3/NF3 and SF6/H2O down‐flow etching. In the NH3/NF3 etching, the wafer was covered with a film, and after its removal by heating above 100 °C, only SiO2 was found to be etched with an extremely high selectivity with respect to Si. Selective etching of Si oxides has also been obtained for SF6/H2O microwave discharge. In this case, a film of liquid solution containing HF and H2SOx is considered to form on the wafer surface. The selective etching of SiO2 takes place by the dissolved HF just as in the wet etching by an HF solution. The mechanisms of these selective reactions are discussed in detail based on the covalency of Si and SiO2 bondings.

Plasma immersion ion implantation (PI3) apparatus

Abstract: Implantation apparatus for cold cathode plasma immersion ion implantation (C 2 PI 3 ) without a continuous plasma using very short high voltage, low duty cycle ionization pulses, in conjunction with a synchronously produced electron flow to neutralize positively charged wafer surfaces.

Method of producing a thin silicon-on-insulator layer

Abstract: A method of forming a thin silicon SOI layer by wafer bonding, the thin silicon SOI layer being substantially free of defects upon which semiconductor structures can be subsequently formed, is disclosed. The method comprises the steps of: a) providing a first wafer comprising a silicon substrate (10) of a first conductivity type, a diffusion layer (12) of a second conductivity type formed thereon and having a first etch characteristic, a thin epitaxial layer (14) of the second conductivity type formed upon the diffusion layer and having a second etch characteristic different from the first etch characteristic of the diffusion layer, and a thin oxide layer (16) formed upon the thin epitaxial layer; b) providing a second wafer comprising a silicon substrate (18) having a thin oxide layer (20) formed on a surface thereof; c) wafer bonding said first wafer to said second wafer so that said thin oxide layers (16,20) bond to form a thick oxide layer (22); d) removing the silicon substrate (10) of said first wafer in a controlled mechanical manner; and e) removing the diffusion layer (12) of said first wafer using a selective dry low energy plasma process to expose the underlying thin epitaxial layer (14), the selective dry low energy plasma process providing an etch ratio of the first etch characteristic to the second etch characteristic such that the diffusion layer is removed with minimal formation of any shallow plasma radiation damage to the exposed underlying thin epitaxial layer. The exposed thin epitaxial layer (14) may be then used as standard to form active/passive devices.

Low-pressure chemical vapor deposition process for depositing high-density highly-conformal, titanium nitride films of low bulk resistivity

Abstract: A low-pressure chemical vapor deposition process is disclosed for creating high-density, highly-conformal titanium nitride films which have very low bulk resistivity, and which provide excellent step coverage. The process utilizes a metal-organic compound, tetrakis-dialkylamido-titanium Ti(NR2)4, as the primary precursor, in combination with an activated species which attacks the alkyl-nitrogen bonds of the primary precursor, and which will convert the displaced alkyl groups into a volatile compound. Any noble gas, as well as nitrogen or hydrogen, or a mixture of two or more of the foregoing may be used as a carrier for the precursor. The activated species, which may include a halogen, NH3, or hydrogen radicals, or a combination thereof, are generated in the absence of the primary precursor, at a location remote from the deposition chamber. The wafer is heated to a temperature within a range of 200°-600° C. The primary precursor molecules and the activated species are mixed, preferably, just prior to being ducted into the deposition chamber. Relatively uncontaminated titanium nitride deposits on the heated wafer surface.

System and method for automated positioning of a substrate in a processing chamber

Abstract: The disclosure relates to a processing apparatus having a central transfer chamber (2); a plurality of peripheral chambers (3a, 3b) positioned around the periphery of said central transfer chamber; and a micro-processor controlled wafer transfer robot (4) disposed in said transfer chamber and having a wafer support (4a) for loading, moving and unloading wafer to and from said peripheral chambers. The wafer support is moved within said central transfer chamber generally along an arcuate path between the peripheral chambers. Reference signals are generated indicative of the position of a wafer support reference point (4c) by a sensor array (6, 8) having at least two sensors mounted along an axis generally transverse to the arcuate path which are triggered by the leading and trailing edges of the moving wafer as it passes to develop corresponding wafer position signals from which a wafer position reference point can be determined. The micro-processor (12) receiving wafer support reference signals and wafer position signals, calculates the location of the wafer relative to the wafer support, and controls movement of the the wafer support to a corresponding offset position relative to a preselected location (65a, 65b) in a peripheral chamber so as to position the wafer accurately at the preselected location in one of the peripheral chambers (3a, 3b).

Selective metal electrodeposition process and apparatus

Abstract: A process and apparatus for advanced semiconductor applications which involves the selective electrodeposition of metal on a semiconductor wafer is described. The present invention has significant economic and performance advantages over the current state of the art. It addresses problems associated with cleanliness (a major issue with sub-micron processing), metal thickness uniformity, step coverage and environmental concerns. A metal with better device performance capabilities compared to the standard aluminum is also employed. The hardware allows the selective deposition to occur without allowing the electrolyte to contact the rear of the wafer or the electrodes contacting the front wafer surface. A virtual anode improves the primary current distribution improving the thickness uniformity while allowing optimization of other film parameters with the remaining deposition variables. Using this process and the associated hardware, metal lines are selectively deposited with contacts or vias completely filled without the need for plasma etching the deposited metal.

Multi-station semiconductor processor with volatilization

Abstract: Disclosed are apparatuses and methods for improved processing of semiconductor wafers and the like using vapor phase processing chemicals, particularly aqueous hydrofluoric acid etchants. Homogeneous vapor mixtures are generated from homogeneous liquid mixtures. Means for recirculating, mixing and agitating the liquid phase reactants are provided. In some embodiments the liquid phase is advantageously circulated through a chemical trench within the processing bowl. Exposure of wafers to vapors from the chemical trench can be controlled by a vapor control valve which is advantageously the bottom of the processing chamber. The wafer is rotated or otherwise moved within the processing chamber to provide uniform dispersion of the homogeneous reactant vapors across the wafer surface and to facilitate vapor circulation to the processed surface. A radiative volatilization processor can be utilized to volatilize reaction by-products which form under some conditions. The apparatuses provide efficient uniform etching with low particle count performance.

Apparatus and method for determining wafer temperature using pyrometry

Abstract: In a RTP reactor where wafer temperature is measured by a pyrometer assembly (32), a pyrometer assembly (50) is further provided to measure the temperature of the quartz window (30) that is situated between the wafer pyrometer assembly (32) and the wafer (16) that is being processed. During the calibration procedure (100, 120) where a thermocouple wafer is used, the measurements from the wafer pyrometer assembly (32) and the window pyrometer assembly (50) are calibrated, and pyrometer measurements and thermocouple measurements are collected and compiled into calibration tables. During actual RTP reactor operation, the data from the calibration tables and current wafer and window pyrometer measurements are used to compute corrected wafer temperature(s). The corrected wafer temperature(s) is/are then used to control the intensities of the heating lamps according to the wafer processing heating schedule.

A new method for measuring the strength and ductility of thin films

Abstract: A new method of measuring the mechanical strength of thin films is described. We prepare miniature arrays of four tensile specimens, each 0.25 mm wide, 1 mm long, and 2.2 μm thick, using deposition, patterning, and etching processes common to the semiconductor industry. Each array of four specimens is carried on and protected by a rectangular silicon frame. Thirty-six such specimens are produced on a single wafer. After a specimen frame is mounted, its vertical sides are severed without damaging the specimens. The load is applied by micrometers through a special tension spring. Tensile properties of a 2.2 μm thick Ti–Al–Ti film were determined.

Programmable semiconductor wafer for sensing, recording and retrieving fabrication process conditions to which the wafer is exposed

Abstract: A semiconductor wafer is provided for sensing and recording processing conditions to which the wafer is exposed. The wafer can also write the recorded processing conditions to an external output device connectable to the wafer. The wafer includes a plurality of regions spaced across the wafer, and at least one sensor placed within each region. The sensor can sense a single processing condition such as, e.g., pressure, temperature, fluidic flow rate, or gas composition. If more than one processing condition is to be measured, then more than one sensor can be placed in each region to provide a sensed reading across the entire wafer surface necessary for gradient measurements. The wafer further includes signal acquisition/conditioning circuit which receives analog signals from each of the sensors placed upon the wafer and converts the analog signals to corresponding digital signals. Digital signals can then be stored within and processed by a processor also formed within the wafer. The semiconductor wafer further includes input/output probe pads which receive external input to the wafer circuitry and output stored information from the circuitry.

Apparatus and method for uniformly polishing a wafer

Abstract: An apparatus and method for polishing a semiconductor wafer. A polisher includes a supporting plate having a conductive film and a polishing cloth formed on the conductive film of the supporting plate. The polishing cloth has a plurality of openings to expose the conductive film. A wafer holder has a conductive wafer holding surface to hold a semiconductor wafer having current detective patterns and an insulating film covering the current detective patterns. A polishing slurry supply device supplies a polishing slurry including ions to either the polishing cloth or the semiconductor wafer. A current detecting device, connected to the supporting plate and the wafer holder, detects a magnitude of a current flowing across the supporting plate and the wafer holder through the conductive wafer holding surface, the semiconductor wafer held by the wafer holder, the current detective patterns of the semiconductor wafer, the polishing slurry filled in the openings of the polishing cloth, and the conductive film.

Stage having electrostatic chuck and plasma processing apparatus using same

Abstract: The plasma etching apparatus for a semiconductor wafer includes a susceptor provided in the vacuum process chamber. An electrostatic chuck for attracting and holding the wafer is provided on the susceptor. The electrostatic chuck comprises a chuck electrode provided on the susceptor via an insulative layer. The chuck electrode is connected to the positive terminal of the DC power supply via a switch. The chuck electrode is coated with a resistive layer, and the wafer is placed directly on the resistive layer. The resistive layer exhibits an electric resistivity of 1×10 10 Ω·cm to 1×10 12 Ω·cm in a temperature range for etching. The resistive layer is formed to have such a surface roughness that a center line average hight falls within a range of 0.1 to 1.5 μm. When the potential of the positive terminal of the DC power supply is applied to the chuck electrode, and the wafer is grounded via plasma, a contact potential difference is created between the surface of the resistive layer and the rear surface of the wafer, generating an electrostatic attractive force, so that the wafer is attracted and held by the resistive layer.

Substrate processing apparatus and substrate processing method

Abstract: A substrate such as a semiconductor wafer is transferred to a plurality of process chambers so as to perform prescribed processes. An inspection chamber is air-tightly connected to each of the process chambers. The inspection chamber is provided with a handler which loads and unloads the substrate. A gate valve is disposed between each process chamber and the inspection chamber. By this gate valve, each chamber is air-tightly closed.

Final polishing composition

Abstract: A final polishing composition for polishing a silicon wafer used as a substrate crystal in electrical integrated circuits comprises water, colloidal silica, a water-soluble polymeric compound, and a water-soluble salt.

Contact type temperature measuring method

Abstract: PURPOSE:To measure the temperature with little measuring error and high reliability by lessening the effect of the measurement environments and the surface condition of a measurement object. CONSTITUTION:A thermally conductive cap 40 to have a touch with the back side of a semiconductor wafer 12 is fixed at the tip part of a thermocouple 38. The thermally conductive cap 40 is made of a material such as silver, copper, brass, diamond, etc., having a high thermal conductivity and is composed of a disk contacting part 40a, a socket part 40c, and a taper part 40d. The disk contacting part 40a receives heat from the semiconductor wafer 12 in the whole upper surface. The heat from the semiconductor wafer 12 received by the disk contacting part 40a is converged and averaged and transmitted to a temperature measuring contact part 38a of the thermocouple 38 through a set (fixed) contacting face in the inside of a probing hole 40b. The thermocouple 38 converts the temperature sensed by the temperature measuring contact part 38a into thermoelectromotive force and sends it as an electric signal to a temperature measuring circuit.