Showing papers on "Wafer published in 1996"

Ultra high throughput wafer vacuum processing system

Abstract: The present invention generally provides a cassette-to-cassette vacuum processing system which concurrently processes multiple wafers and combines the advantages of single wafer process chambers and multiple wafer handling for high quality wafer processing, high wafer throughput and reduced footprint. In accordance with one aspect of the invention, the system is preferably a staged vacuum system which generally includes a loadlock chamber for introducing wafers into the system and which also provides wafer cooling following processing, a transfer chamber for housing a wafer handler, and one or more processing chambers each having two or more processing regions which are isolatable from each other and preferably share a common gas supply and a common exhaust pump. The processing regions also preferably include separate gas distribution assemblies and RF power sources to provide a uniform plasma density over a wafer surface in each processing region. The processing chambers are configured to allow multiple, isolated processes to be performed concurrently in at least two processing regions so that at least two wafers can be processed simultaneously in a chamber with a high degree of process control provided by shared gas sources, shared exhaust systems, separate gas distribution assemblies, separate RF power sources, and separate temperature control systems.

Use of cobalt tungsten phosphide as a barrier material for copper metallization

Abstract: A technique for electrolessly depositing a CoWP barrier material on to copper and electrolessly depositing copper onto a CoWP barrier material to prevent copper diffusion when forming layers and/or structures on a semiconductor wafer.

Surface activated bonding of silicon wafers at room temperature

Abstract: A method to bond silicon wafers directly at room temperature was developed. In this method, surfaces of two silicon samples are activated by argon atom beam etching and brought into contact in a vacuum. By the infrared microscope and KOH etching method, no void at the bonded interface was detected in all the specimens tested. In the tensile test, fracture occurred not at the interface but mainly in the bulk of silicon. From these results, it is concluded that the method realizes strong and tight bonding at room temperature and is promising to assemble small parts made by the silicon wafer process.

Method of modifying an exposed surface of a semiconductor wafer

Abstract: A method of modifying an exposed surface of a semiconductor wafer that includes the steps of: (a) contacting the surface with a fixed abrasive article having a three-dimensional textured abrasive surface that includes a plurality of abrasive particles and a binder in the form of a pre-determined pattern; and (b) relatively moving the wafer and the fixed abrasive article to modify said surface of the wafer.

Absorption enhancement in silicon‐on‐insulator waveguides using metal island films

Abstract: We report the degree to which the resonances associated with metal island films can be used to enhance the sensitivity of very thin semiconductor photodetectors. The island films can couple incident light into the waveguide modes of the detector, resulting in increased absorption. To characterize the coupling, silver‐, gold‐, and copper‐island layers were formed on the surface of a thin‐film photodetector fabricated in the 0.16 μm thick silicon layer of a silicon‐on‐insulator (SOI) wafer. The copper islands gave the best result, producing more than an order of magnitude enhancement in the photocurrent for light of wavelength 800 nm. The enhancements appear to be due primarily to coupling between the metal island resonances and the waveguide modes supported by the SOI structure.

Thermally floating pedestal collar in a chemical vapor deposition chamber

Abstract: A substrate processing chamber, particularly a chemical vapor deposition (CVD) chamber used both for thermal deposition of a conductive material and a subsequently performed plasma process. The invention reduces thermal deposition of the conductive material on peripheral portions of the pedestal supporting a wafer and in a pumping channel exhausting the chamber. A peripheral ring placed on the pedestal, preferably also used to center the wafer, is thermally isolated from the pedestal so that its temperature is kept substantially lower than that of the wafer. Despite its thermal isolation, the peripheral ring is electrically connected to the pedestal to prevent arcing. The pumping channel is lined with various elements, some of which are electrically floating and which are designed so that conductive material deposited on these elements do not deleteriously affect a plasma generated for processing the wafer.

Electroless CU deposition on a barrier layer by CU contact displacement for ULSI applications

Abstract: A method of utilizing electroless copper deposition to form interconnects on a semiconductor wafer. Once a via or a trench is formed in a dielectric layer, a titanium nitride (TiN) or tantalum (Ta) barrier layer is blanket deposited. Then, a contact displacement technique is used to form a thin activation seed layer of copper on the barrier layer. An electroless deposition technique is then used to auto-catalytically deposit copper on the activated barrier layer. The electroless copper deposition continues until the via/trench is filled. Subsequently, the surface is polished by an application of chemical-mechanical polishing (CMP) to remove excess copper and barrier material from the surface, so that the only copper and barrier material remaining are in the via/trench openings. Then an overlying silicon nitride (SiN) layer is formed above the exposed copper in order to form a dielectric barrier layer. The copper interconnect is fully encapsulated from the adjacent material by the TiN (or Ta) and the SiN layers.

Reduction of hot electron degradation in metal oxide semiconductor transistors by deuterium processing

Abstract: We report experimental results that replacing hydrogen with deuterium during the final wafer sintering process greatly reduces hot electron degradation effects in metal oxide semiconductor transistors due to a new giant isotope effect. Transistor lifetime improvements by factors of 10–50 are observed. A plausible physical theory suggests that the benefits of deuterium use may be general and also applicable to other areas of semiconductor device processing and fabrication.

Application of hydrogen ion beams to Silicon On Insulator material technology

Abstract: A new application for proton ion beams in the field of Silicon On Insulator material (SOI) technology is reported. In this technology, based on hydrophillic wafer bonding and referred to as “Smart-Cut”, heat treatment induces an in-depth micro-slicing of one of two bonded wafers previously implanted with hydrogen. The principle of this process involves the basic mechanisms associated with high fluence proton implantation in materials, such as blistering, flaking and exfoliation. The intrinsic properties of this process lead to very high crystalline quality of the SOI layers and very good thickness uniformity. After presentation of the process details and the underlying physical aspects, the main characteristics of the Smart-Cut technology and first physical and electrical characterizations are reported.

Laser imaging system for inspection and analysis of sub-micron particles

Abstract: A laser imaging system is used to analyze defects on semiconductor wafers that have been detected by patterned wafer defect detecting systems (wafer scanners). The laser imaging system replaces optical microscope review stations now utilized in the semiconductor fab environment to examine detected optical anomalies that may represent wafer defects. In addition to analyzing defects, the laser imaging system can perform a variety of microscopic inspection functions including defect detection and metrology. The laser imaging system uses confocal laser scanning microscopy techniques, and operates under class 1 cleanroom conditions and without exposure of the wafers to operator contamination or airflow. Unlike scanning electron microscopes (SEMs) that have previously been used for defect analysis, the laser imaging system will not damage samples or slow processing, costs significantly less to implement than an SEM, can produce a three dimensional image which provides quantitative dimensional information, and allows sub-surface viewing of defects lying beneath dielectric layers. The laser imaging system is adaptable to cluster or in-situ applications, where examination of defects or structures during on-line processing can be performed.

Symmetric tunable inductively coupled HDP-CVD reactor

Abstract: The present invention provides an HDP-CVD tool using simultaneous deposition and sputtering of doped and undoped silicon dioxide capable of excellent gap fill and blanket film deposition on wafers having sub 0.5 micron feature sizes having aspect ratios higher than 1.2:1. The system of the present invention includes: a dual RF zone inductively coupled plasma source configuration capable of producing radially tunable ion currents across the wafer; a dual zone gas distribution system to provide uniform deposition properties across the wafer surface; temperature controlled surfaces to improve film adhesion and to control extraneous particle generation; a symmetrically shaped turbomolecular pumped chamber body to eliminate gas flow or plasma ground azimuthal asymmetries; a dual helium cooling zone electrostatic chuck to provide and maintain uniform wafer temperature during processing; an all ceramic/aluminum alloy chamber construction to eliminate chamber consumables; and a remote fluorine based plasma chamber cleaning system for high chamber cleaning rate without chuck cover plates.

Area specific temperature control for electrode plates and chucks used in semiconductor processing equipment

Abstract: A temperature control system to selectively control the temperature of specific areas of the chuck or electrode plate upon which a wafer is mounted during plasma etching, chemical vapor deposition and other such temperature dependent processes for the purpose of ultimately controlling the temperature of the semiconductor wafer. The temperature control system includes a plurality of conduits arranged about the center of the chuck as a series of concentric radially adjacent loops. Each conduit is connected to its own inlet and outlet to allow a heating or cooling agent to flow independently through each conduit.

Parallel plate electrode plasma reactor having an inductive antenna and adjustable radial distribution of plasma ion density

Abstract: There is disclosed a plasma reactor for processing a semiconductor workpiece such as a wafer, including a chamber having an overhead ceiling with a three-dimensional shape such as a hemisphere or dome. The reactor further includes an inductive antenna over the ceiling which may be conformal or nonconformal in shape with the ceiling. The ceiling may be a semiconductor material so that it can function as both a window for the inductive field of the antenna as well as an electrode which can be grounded, or to which RF power may be applied or which may be allowed to float electrically. The reactor includes various features which allow the radial distribution of the plasma ion density across the wafer surface to be adjusted to an optimum distribution for processing uniformity across the wafer surface.

Chemical vapor deposition reactor system and integrated circuit

Abstract: A method of and apparatus for depositing a silicon oxide layer onto a wafer or substrate is provided. The present method includes introducing into a processing chamber a process gas including silicon, oxygen, boron, phosphorus and germanium to form a germanium doped BPSG oxide layer having a reflow temperature of less than 800° C. Preferred embodiments of the present method are performed in either a subatmospheric CVD or a plasma enhanced CVD processing apparatus.

Multideck wafer processing system

Abstract: A multideck wafer processing system is described for the treatment of semiconductor wafers. The system includes at least two process chambers stacked one above the other to provide for higher wafer throughput per unit area of cleanroom space. The stacked process chambers enable sharing of pressurization, gas, electrical, and control support services for the processing chambers.

Electrostatic chuck and method of attracting wafer

Abstract: An electrostatic chuck including an electrode having first and second surfaces, a dielectric member having a first layer for covering at least the first surface of the electrode, a power supply for conducting electric power to the electrode, and a cooling gas-feeding means for feeding a cooling gas onto the surface of the first layer of the dielectric member. A plurality of fine projections 28 are formed on the surface of the first layer of the dielectric member. Each of the fine projections 28 has a tip smaller than a root thereof so as to hold a wafer W in substantially a point-contact manner. The wafer can be held on the surface of the first layer of the dielectric member and cooled by the cooling gas fed from the cooling gas-feeding means.

Method for manufacturing a semiconductor acceleration sensor device

Abstract: On a silicon wafer there is formed a movable gate MOS transistor (sensing element: functional element). A bonding frame consisting of a silicon thin film is patterned around an element formation region on the surface of the silicon wafer. On a cap forming silicon wafer there is projectively provided a leg portion on the bottom surface of which a bonding layer consisting of a gold film is formed. The cap forming silicon wafer is disposed on the silicon wafer, whereupon heating with respect thereto is performed at a temperature equal to higher than a gold/silicon eutectic temperature to thereby make bondage between the bonding frame of the silicon wafer and the bonding layer of the cap forming silicon wafer. Thereafter, the both wafers are diced in chip units.

Process for the manufacture of thin films of semiconductor material

Abstract: The process includes the following steps: implantation of ions (12) in a semi-conducting wafer (10), to create a cleavage layer of gaseous microblisters (16) in the wafer, heat treatment of the wafer, in order to cause separation of a surface layer (18) from the rest of the wafer, along the layer of microblisters. According to the invention, the implantation is carried out at a depth equal to or greater than a given minimum depth so that the thin film obtained is rigid, and so that the heat treatment can release it.

Apparatus for reducing process drift in inductive coupled plasma etching such as oxide layer

Abstract: A plasma processing chamber includes a substrate holder and a gas distribution plate having an inner surface facing the substrate holder, the inner surface being maintained below a threshold temperature to minimize process drift during processing of substrates. The inner surface is cooled by adding a heat transfer gas such as helium to process gas supplied through the gas distribution plate. The chamber can include a dielectric window between an antenna and the gas distribution plate. The control of the temperature of the inner surface facing the substrate minimizes process drift and degradation of the quality of the processed substrates during sequential processing of the substrates such as during oxide etching of semiconductor wafers.

Wafer support member

Abstract: A wafer support member comprises a base made of ceramics with thickness of 3 mm or more, a metallic electrode plate with thickness of 0.5 mm or more bonded onto the base, and an attraction surface composed of an aluminum nitride film with thickness of 0.01 to 0.5 mm coated on the surface of the electrode plate. The electrode plate functions as a plasma generating electrode when high frequency voltage is applied to the electrode plate and as an electrostatic attraction electrode when direct-current high voltage is applied to the electrode plate. Also, a wafer holding device for holding a wafer such as semiconductor wafer and glass substrate for liquid crystal is disclosed. The wafer holding device comprises a base body of aluminum nitride sintered body containing resistance heating elements therein. Lead terminals for feeding power to the resistance heating elements are formed in the lower surface of the base body. In one feature, at least the lead terminals and junction thereof are coated with a ceramic film composed of any one of silicon carbide, silicon nitride, sialon, and aluminum nitride. In another feature, the base body has a flat surface for forming an attraction surface, an outer circumference and penetration holes. Each of the penetration holes opens in the flat surface, and has an inner wall. An aluminum nitride film covers the flat surface, the outer circumference, and the inner wall of each of the penetration holes.

System and method for thermal processing of a semiconductor substrate

Abstract: A semiconductor substrate processing system and method using a stable heating source with a large thermal mass relative to conventional lamp heated systems. The system dimensions and processing parameters are selected to provide a substantial heat flux to the wafer while minimizing heat loss to the surrounding environment (particularly from the edges of the heat source and wafer). The heat source provides a wafer temperature uniformity profile that has a low variance across temperature ranges at low pressures. A resistively heated block is substantially enclosed within an insulated vacuum cavity used to heat the wafer. A vacuum region is preferably provided between the heated block and the insulating material as well as between the insulating material and the chamber wall. Heat transfer across the vacuum regions is primarily achieved by radiation, while heat transfer through the insulating material is achieved by conduction. The wafer is placed on or near the heated block within the vacuum cavity for heating by conduction and radiation. The rate of heating may be controlled by varying pressure across a range of very low pressures.

Use of palladium immersion deposition to selectively initiate electroless plating on Ti and W alloys for wafer fabrication

Abstract: A method for making integrated circuit wafers wherein the wafer has vias or other openings in the wafer which openings have a barrier/adhesion or other metal layer which is metallized to form the circuit comprising activating the metal layer and then sensitizing the metallic layer using a sensitizing displacement composition comprising preferably an alkaline palladium non-ammonia nitrogen (ethylene diamine) complex which is contacted with the wafer at a specially controlled pH. The wafer is activated using an activation solution which contains a complexing agent for any dissolved metal. The sensitizing solution also preferably contains a complexing agent for dissolved metal and preferably contains a second complexing agent such as EDTA to solubilize base metal contaminants.

Spin cleaning method

Abstract: At first, a semiconductor wafer is held and rotated by a spin chuck, and supplied with a hydrofluoric acid solution from a chemical liquid nozzle to remove natural oxide films on the wafer. Then, the wafer is supplied with pure water for rinsing it from a rinsing nozzle while the wafer is rotated. Right before the pure water stops being supplied, the wafer is supplied with an IPA liquid from a replacing medium nozzle while the wafer is rotated. The pure water is replaced with the IPA liquid by means of the Marangoni effect and a centrifugal force. Then, the wafer is rotated at 300 rpm for one second, at 3000 rpm for four seconds, and at 5000 rpm for five seconds, in this order, to remove the IPA liquid by means of a centrifugal force.

Semiconductor wafer processing adhesives and tapes

Abstract: A semiconductor wafer processing tape comprises a permanent backing and a layer of a non-pressure sensitive adhesive comprising a thermoplastic elastomer block copolymer on the permanent backing. Optionally, the adhesive may include an adhesion modifier such as a tackifying resin, a liquid rubber or a photocrosslinking agent. The tapes are useful for both wafer grinding and wafer dicing applications. A method of processing semiconductor wafers is disclosed.

Stable and efficient electroluminescence from a porous silicon‐based bipolar device

Abstract: A complete process compatible with conventional Si technology has been developed in order to produce a bipolar light‐emitting device. This device consists of a layer of light‐emitting porous silicon annealed at high temperature (800–900 °C) sandwiched between a p‐type Si wafer and a highly doped (n+) polycrystalline Si film. The properties of the electroluminescence (EL) strongly depend on the annealing conditions. Under direct bias, EL is detected at voltages of ∼2 V and current densities J∼1 mA/cm2. The maximum EL intensity is 1 mW/cm2 and the EL can be modulated by a square wave current pulse with frequencies ν≥1 MHz. No degradation has been observed during 1 month of pulsed operation.

Role of etch products in polysilicon etching in a high-density chlorine discharge

Abstract: For low-pressure, high-density plasma systems, etch products can play a significant role in affecting plasma parameters such a.s species concentration and electron temperature. The residence time of etch products in the chamber can he long, hence depleting the concentration of the reactants, and leading to a decrease in etch rate. We use a spatially averaged global model including both gas phase and surface chemistry to study Cl2 etching of polvsilicon. Etch products leaving the wafer surface are assioned to he SiCL2 and SiCl4. These species can be fragmented and ionized by collisions with energetic electrons, generating neutral and charged SiCl, products (x=0–4). Two limiting cases of the etch mechanism are found. an ion flux-limited regime and a neutral reactant-limited regime. The high degree of dissociation in high-density plasmas leads to the formation of elemental silicon, which can deposit on the chamber walls and wafer surface. We include surface models for both the wall and the wafer to better understand the role of etch products as a function of flowrate, pressure, and input pwer. A phenomenological model for the surface chemistry is based on available experimental data. We consider the two limiting conditions of nonreactive and reactive walls. These models are perfectly reflective walls, where all silicon-containing species are reflected; and reactive walls, which act as reactive sites for the formation of SiCl2 and SiCl4 etch products. The two limiting conditions give significantly different results. A decrease in the absolute atomic silicon density and a weaker dependence of etch rate on flowrate are observed for the reactive wall.

Method and apparatus for dicing semiconductor wafers

Abstract: A method and apparatus for dicing semiconductor wafers is provided. The method comprises: forming an etch mask on the wafer, and then etching the wafer with a wet etchant, such as KOH, to form a peripheral groove around each die. Etching the wafer can be from the front side of the wafer, from the back side of the wafer or with partial etches from both sides. The etch process can be performed on a single wafer using a spray head apparatus or on batches of wafers using a recirculating dip tank apparatus.

Process for laser detection of gas and contaminants in a wafer transport gas tunnel

Abstract: A process of using a transport system for transporting substrate wafer, for making semiconductor integrated circuits and liquid crystal display panels and the like advanced devices, is presented. The object is to prevent surface degradation which may be inflicted on the surface to interfere with proper processing of the substrate. The substrate wafers are delivered to process chambers always in clean surface conditions. A method illustrated utilizes a purge gas containing an inert gas or a mixture of an inert gas and oxygen for flowing inside the tunnel space, and a semiconductor laser detection system to detect the contamination levels within the tunnel space, and the transport parameters are controlled according to the measured data.

Wafer positioning system

Abstract: A wafer positioning system determines the position of a wafer during processing by monitoring the position of the wafer transport robot as the robot transports the wafer by one or more position sensors. The wafer positioning system incorporates a transparent cover on the surface of the wafer handling chamber and two optical position sensors disposed on the surface of the transparent cover. The position sensors direct light through the wafer handling chamber to reflectors near the floor of the chamber which reflect the light back to the position sensors. A detector within the position sensor detects when the beam path from the position sensor to the reflector is uninterrupted. As wafers are transported through the chamber, the edge of the transported wafer interrupts the position sensor beam path causing the output of the position sensor to switch states. When the position sensor output switches, the position of the wafer transport robot is measured. At least two data points are measured to establish the wafer position. If the wafer is not at its nominal position, the position of the wafer transport robot is adjusted to compensate for the wafer misalignment.

LPCVD silicon‐rich silicon nitride films for applications in micromechanics, studied with statistical experimental design*

Abstract: A systematic investigation of the influence of the process parameters temperature, pressure, total gas flow, and SiH2Cl2:NH3 gas flow ratio on the residual stress, the refractive index, and its nonuniformity across a wafer, the growth rate, the film thickness nonuniformity across a wafer, and the Si/N incorporation ratio of low pressure chemical vapor deposition SixNy films has been performed. As a tool for complete characterization of the property-deposition parameter relations, a full factorial experimental design was used to determine the dominant process parameters and their interactions. From this study it could be concluded that, in decreasing order of importance, the gas flow ratio of Si and N containing precursors, temperature, and pressure are the most relevant parameters determining the mechanical and optical properties of the films and the deposition rate and nonuniformity in film properties across a wafer. The established relations between properties and deposition parameters were fitted with physical–chemical models, including a film growth model based on a Freundlich adsorption isotherm. The optimal deposition conditions for films to be used in micromechanical devices will be discussed.