Showing papers on "Wafer published in 1998"

A three-dimensional photonic crystal operating at infrared wavelengths

Abstract: The ability to confine and control light in three dimensions would have important implications for quantum optics and quantum-optical devices: the modification of black-body radiation, the localization of light to a fraction of a cubic wavelength, and thus the realization of single-mode light-emitting diodes, are but a few examples1,2,3. Photonic crystals — the optical analogues of electronic crystal — provide a means for achieving these goals. Combinations of metallic and dielectric materials can be used to obtain the required three-dimensional periodic variations in dielectric constant, but dissipation due to free carrier absorption will limit application of such structures at the technologically useful infrared wavelengths4. On the other hand, three-dimensional photonic crystals fabricated in low-loss gallium arsenide show only a weak ‘stop band’ (that is, range of frequencies at which propagation of light is forbidden) at the wavelengths of interest5. Here we report the construction of a three-dimensional infrared photonic crystal on a silicon wafer using relatively standard microelectronics fabrication technology. Our crystal shows a large stop band (10–14.5 μm), strong attenuation of light within this band (∼12 dB per unit cell) and a spectral response uniform to better than 1 per cent over the area of the 6-inch wafer.

Method for manufacturing a semiconductor device

Abstract: A semiconductor wafer, which can be divided into chips at a high yield and a low cost and easily handled during transfer thereof as well, is disclosed. In a semiconductor wafer of such structure that structures with a low mechanical strength, such as suspended microstructures, are exposed at a surface thereof, detachable adhesive sheet making up protective caps for the respective suspended microstructures are formed over the semiconductor wafer. By means of this, even if the semiconductor wafer is diced into the individual chips, respective microstructures on chips are protected from the external force, such as the pressure of cutting water, during the dicing process.

Semiconductor wafer bonding

Abstract: When mirror-polished, flat, and clean wafers of almost any material are brought into contact at room temperature, they are locally attracted to each other by van der Waals forces and adhere or bond. This phenomenon is referred to as wafer bonding. The most prominent applications of wafer bonding are silicon-on-insulator (SOI) devices, silicon-based sensors and actuators, as well as optical devices. The basics of wafer-bonding technology are described, including microcleanroom approaches, prevention of interface bubbles, bonding of III-V compounds, low-temperature bonding, ultra-high vacuum bonding, thinning methods such as smart-cut procedures, and twist wafer bonding for compliant substrates. Wafer bonding allows a new degree of freedom in design and fabrication of material combinations that previously would have been excluded because these material combinations cannot be realized by the conventional approach of epitaxial growth.

SemiConductor Wafer Bonding: Science and Technology

Abstract: Basics of Interactions Between Flat Surfaces. Influence of Particles, Surface Steps, and Cavities. Surface Preparation and Room-Temperature Wafer Bonding. Thermal Treatment of Bonded Wafer Pairs. Thinning Procedures. Electrical Properties of Bonding Interfaces. Stresses in Bonded Wafers. Bonding of Dissimilar Materials. Bonding of Structured Wafers. Mainstream Applications. Emerging and Future Applications. Index.

Wafer-to-wafer bonding for microstructure formation

Abstract: Wafer-to-wafer bonding processes for microstructure fabrication are categorized and described. These processes have an impact in packaging and structure design. Processes are categorized into direct bonds, anodic bonds, and bonds with intermediate layers. Representative devices using wafer-to-wafer bonding are presented. Processes and methods for characterization of a range of bonding methods are discussed. Opportunities for continued development are outlined.

Method and apparatus for scheduling wafer processing within a multiple chamber semiconductor wafer processing tool having a multiple blade robot

Abstract: Apparatus and concomitant method for performing priority-based scheduling of wafer processing within a multiple chamber semiconductor wafer processing system (cluster tool) having a dual blade wafer transfer mechanism. The sequencer assigns priority values to the chambers in a cluster tool, then moves wafers from chamber to chamber in accordance with the assigned priorities. The sequencer is capable of determining the amount of time available before a priority move is to be performed and, if time is sufficient, the sequencer performs a non-priority move while waiting. The sequencer also dynamically varies assigned priorities depending upon the availability of chambers in the tool. Lastly, the sequencer prioritizes the chambers based upon the minimum time required for the wafer transfer mechanism to move the wafers in a particular stage.

Design rule checking system and method

Abstract: A method for performing design rule checking on OPC corrected or otherwise corrected designs is described. This method comprises accessing a corrected design and generating a simulated image. The simulated image corresponds to a simulation of an image which would be printed on a wafer if the wafer were exposed to an illumination source directed through the corrected design. The characteristics of the illumination source are determined by a set of lithography parameters. In creating the image, additional characteristics can be used to simulate portions of the fabrication process. However, what is important is that a resulting simulated image is created. The simulated image can then be used by the design rule checker. Importantly, the simulated image can be processed to reduce the number of vertices in the simulated image, relative to the number of vertices in the OPC corrected design layout. Also, the simulated image can be compared with an idea layout image, the results of which can then be used to reduce the amount of information that is needed to perform the design rule checking.

Fabrication of single-crystal lithium niobate films by crystal ion slicing

Abstract: We report on the implementation of crystal ion slicing in lithium niobate (LiNbO3). Deep-ion implantation is used to create a buried sacrificial layer in single-crystal c-cut poled wafers of LiNbO3, inducing a large etch selectivity between the sacrificial layer and the rest of the sample. 9-μm-thick films of excellent quality are separated from the bulk and bonded to silicon and gallium arsenide substrates. These single-crystal films have the same room-temperature dielectric and pyroelectric characteristics, and ferroelectric transition temperature as single-crystal bulk. A stronger high-temperature pyroelectric response is found in the films.

Method and apparatus for automatically generating schedules for wafer processing within a multichamber semiconductor wafer processing tool

Abstract: A method and apparatus for producing schedules for a wafer in a multichamber semiconductor wafer processing tool comprising the steps of providing a trace defining a series of chambers that are visited by a wafer as the wafer is processed by the tool; initializing a sequence generator with a vertex defining initial wafer positioning within the tool; generating all successor vertices to produce a series of vectors interconnecting the vertices that, when taken together produce a cycle that represents a schedule. All the possible schedules are analyzed to determine a schedule that produces the highest throughput of all the schedules.

Method of planarizing the upper surface of a semiconductor wafer

Abstract: This invention pertains to a method of modifying or refining a surface of a wafer suited for semiconductor fabrication. This method may be used to modify a wafer having an unmodified, exposed surface comprised of a layer of a second material deployed over at least one discrete feature of a first material attached to the wafer. A first step of this method comprises contacting and relatively moving the exposed surface of the wafer with respect to an abrasive article, wherein the abrasive article comprises an exposed surface of a plurality of three-dimensional abrasive composites comprising a plurality of abrasive particles fixed and dispersed in a binder and maintaining contact to effect removal of the second material. In a second step, the contact and relative motion are continued until an exposed surface of the wafer has at least one area of exposed first material and at least one area of exposed second material.

Multiple beams and nozzles to increase deposition rate

Abstract: An apparatus and method have been developed to exploit the desirable material and process characteristics provided by a low powered laser material deposition system, while overcoming the low material deposition rate imposed by the same process. One application of particular importance for this invention is direct fabrication of functional, solid objects from a CAD solid model. This apparatus uses a software interpreter to electronically slice the CAD model into thin horizontal layers that are subsequently used to drive the deposition apparatus. This apparatus uses a single laser beam to outline the features of the solid object and then uses a series of equally spaced laser beams to quickly fill in the featureless regions. Using the lower powered laser provides the ability to create a part that is very accurate, with material properties that meet or exceed that of a conventionally processed and annealed specimen of similar composition. At the same time, using the multiple laser beams to fill in the featureless areas allows the fabrication process time to be significantly reduced.

Pattern of apertures in a showerhead for chemical vapor deposition

Abstract: A showerhead used for dispensing gas over a wafer in chemical vapor deposition (CVD), especially for CVD of metals. The patterns of holes is tailored to compensate for thermal and other effects, in particular by increasing the density of holes toward the periphery of the wafer in three or more zones. Such a variable pattern is particularly useful for liquid precursors that are atomized in a carrier gas, in which case a second perforated plate in back of the showerhead face can be eliminated, thereby reducing the flow impedance and the required pressure of the liquid-entrained gas, which tends to deposit out at higher pressures. The reduce flow impedance is particularly useful for CVD of copper.

Method of dividing a wafer and method of manufacturing a semiconductor device

Abstract: Grooves are formed in a surface of a wafer, on which surface semiconductor elements are formed, along dicing lines. The grooves are deeper than a thickness of a finished chip. A holding member is attached on the surface of the wafer on which the semiconductor elements are formed. A bottom surface of the wafer is lapped and polished to the thickness of the finished chip, thereby dividing the wafer into chips. When the wafer is divided into the chips, the lapping and polishing is continued until the thickness of the wafer becomes equal to the thickness of the finished chip, even after the wafer has been divided into the chips by the lapping and polishing.

Deposition of copper with increased adhesion

Abstract: A method and apparatus for improving the adhesion of a copper layer to an underlying layer on a wafer. The layer of copper is formed over a layer of material on a wafer and the copper layer impacted with ions to improve its adhesion to the underlying layer.

A “smarter-cut” approach to low temperature silicon layer transfer

Abstract: Silicon wafers were first implanted at room temperature by B+ with 5.0×1012 to 5.0×1015 ions/ cm2 at 180 keV, and subsequently implanted by H2+ with 5.0×1016 ions/cm2 at an energy which locates the H-peak concentration in the silicon wafers at the same position as that of the implanted boron peak. Compared to the H-only implanted samples, the temperature for a B+H coimplanted silicon layer to split from its substrate after wafer bonding during a heat treatment for a given time is reduced significantly. Further reduction of the splitting temperature is accomplished by appropriate prebonding annealing of the B+H coimplanted wafers. Combination of these two effects allows the transfer of a silicon layer from a silicon wafer onto a severely thermally mismatched substrate such as quartz at a temperature as low as 200 °C.

Method of high density plasma CVD gap-filling

Abstract: A gap filling process of depositing a film of SiO2 in gaps on a substrate by generating plasma in a process chamber by energizing gas containing silicon, oxygen and a heavy noble gas such as xenon or krypton. The gaps can have widths below 0.5 μm and aspect ratios higher than 1.5:1. A substrate is supported on a substrate support wherein a gas passage supplies a temperature control gas into a space between opposed surfaces of the substrate and the substrate support, and the film is grown in the gaps on the substrate by contacting the substrate with the plasma. The silicon reactant can be SiH4 and the oxygen reactant can be pure oxygen gas supplied by O2 /SiH4 ratio of ≦1.05. The plasma can be a high density plasma produced in an ECR or TCP reactor and the substrate can be a silicon wafer including aluminum conductor lines.

UV exposure for improving properties and adhesion of dielectric polymer films formed by chemical vapor deposition

Abstract: An ultraviolet-assisted chemical vapor deposition system for improving the adhesion, hardness, and thermal stability of organic polymer films deposited on semiconductor wafers is provided. The system includes an ultraviolet lamp and a tube-shaped monomer distribution system positioned over the wafer allowing ultraviolet irradiation of the wafer before, during and/or after deposition. Processes for depositing organic polymer films on semiconductor wafers are also provided. The processes include one or more depositions, one or more ultraviolet exposures, and one or more anneals.

Method and apparatus for detecting the endpoint in chemical-mechanical polishing of semiconductor wafers

Abstract: A method and apparatus for detecting the endpoint of CMP processing on semiconductor wafer in which a lower layer of material with a first reflectivity is positioned under an upper layer of material with a second reflectivity. Initially an endpoint site is selected on the wafer in a critical area where a boundary between the upper and lower layers defines the desired end point of the CMP process. The critical area on the wafer is generally determined by analyzing in the circuit design and the polishing characteristics of previously polished test wafers to denote the last points on the wafer from which the upper layer is desirably removed by CMP processing. After an endpoint site is selected, a light beam impinges the polished surface of the wafer and reflects off of the surface of the wafer to a photosensor. The photosensor senses the actual intensity of the reflected light beam. The actual intensity of the reflected light beam is compared with an expected intensity to determine whether the upper layer has been adequately removed from the endpoint site. The actual intensity is preferably compared with an expected intensity for light reflected from one of the upper or lower layers, and the endpoint is preferably detected when the actual intensity of the reflected light beam is either substantially the same as the expected intensity for light reflected from the lower layer or substantially different from the expected intensity for light reflected from the upper layer.

Comprehensive characterization of metal–semiconductor–metal ultraviolet photodetectors fabricated on single-crystal GaN

Abstract: We report on the material, electrical, and optical properties of metal–semiconductor–metal ultraviolet photodetectors fabricated on single-crystal GaN, with active layers of 1.5 and 4.0 μm thickness. We have modeled current transport in the 1.5 μm devices using thermionic field emission theory, and in the 4.0 μm devices using thermionic emission theory. We have obtained a good fit to the experimental data. Upon repeated field stressing of the 1.5 μm devices, there is a degradation in the current–voltage (I–V) characteristics that is trap related. We hypothesize that traps in the GaN are related to a combination of surface defects (possibly threading dislocations), and deep-level bulk states that are within a tunneling distance of the interface. A simple qualitative model is presented based on experimental results. For devices fabricated on wafers with very low background free electron concentrations, there is a characteristic “punch-through” voltage, which we attribute to the interaction of the depletion ...

Spatial characterization of doped SiC wafers by Raman spectroscopy

Abstract: Raman spectroscopy has been used to investigate wafers of both 4H–SiC and 6H–SiC. The wafers studied were semi-insulating and n-type (nitrogen) doped with concentrations between 2.1×1018 and 1.2×1019 cm−3. Significant coupling of the A1 longitudinal optical (LO) phonon to the plasmon mode was observed. The position of this peak shows a direct correlation with the carrier concentration. Examination of the Raman spectra from different positions on the wafer yielded a rudimentary spatial map of the carrier concentration. These data are compared with a resistivity map of the wafer. These results suggest that Raman spectroscopy of the LO phonon–plasmon mode can be used as a noninvasive, in situ diagnostic for SiC wafer production and substrate evaluation.

High density plasma enhanced chemical vapor deposition process in combination with chemical mechanical polishing process for preparation and planarization of intemetal dielectric layers

Abstract: A wafer planarization process which utilizes combined high density plasma chemical vapor deposition (HDP-CVD) process and chemical mechanical polishing (CMP) process is disclosed. This process includes the steps of (a) forming a first HDP-CVD layer on the surface of a semiconductor wafer using a first HDP-CVD composition having a higher etching/depositing component ratio and thus a lower CMP removal rate; (b) forming a second HDP-CVD layer on the first HDP-CVD layer using the same HDP-CVD process but with a second HDP-CVD composition having a lower etching/depositing component ratio and thus a higher CMP removal rate; and (c) using a chemical mechanical process to remove at least a part of the second HDP-CVD layer using the first HDP-CVD layer as a stopper. A protective layer with the same etching/deposition components but a different ratio than the sacrificial layer can be deposited on the sacrificial layer to minimize the dishing effect during the initial stage of the chemical mechanical polishing process.

Clamshell apparatus for electrochemically treating semiconductor wafers

Abstract: An apparatus for electroplating a wafer surface includes a cup (34J) having a central aperture defined by an inner perimeter (A25), a compliant seal (F25) adjacent the inner perimeter, contacts (D25) adjacent the compliant seal and a cone attached to a rotatable spindle. The compliant seal forms a seal with the perimeter region of the wafer surface preventing plating solution from contaminating the wafer edge, wafer backside and the contacts. As a further measure to prevent contamination, the region behind the compliant seal is pressurized. By rotating the wafer during electroplating, bubble entrapment on the wafer surface is prevented. Further, the contacts can be arranged into banks of contacts and the resistivity between banks can be tested to detect poor electrical connections between the contacts and the wafer surface.

A novel micromachined pump based on thick-film piezoelectric actuation

Abstract: A new silicon-based micropump is described in this paper. The key element of the device is a thick-film/silicon micromachined hybrid actuator. The actuation principle relies on the flexure of a screen printed piezoelectric lead zirconate titanate (PZT) layer on a silicon membrane (8 mm × 4 mm × 70 μm). An investigation into the deposition technology of the bottom electrode for the piezoelectric material showed that a gold resinate or Pt evaporated electrode on a 500 nm thick SiO 2 covered silicon wafer achieved best results for the membrane actuator. Inlet and outlet valves are of the cantilever type and use deep boron diffusion together with KOH etching. Pump rates of up to 120 μl min −1 have been achieved. A maximum backpressure of 2 kPa was measured when using a 600 V pp sinusoidal drive voltage at 200 Hz across a 100 μm thick PZT layer. The pump was compared with a conventional surface mounted piezoelectric driven micropump. The conventional pump achieves a performance which was a factor of 3–6 more efficient, but does not allow mass production.

Electronic device pad relocation, precision placement, and packaging in arrays

Abstract: Top die pads are electrically relocated by forming holes through a semiconductor wafer between device active regions. An electrically insulating layer is formed over all exposed surfaces of the wafer, including within the holes, and openings are made in the insulating layer for access to the top interconnection pads. The wafer and holes are metallized and patterned to form bottom interconnection pads electrically connected to corresponding top interconnection pads by metallization extending within the holes. A dicing saw having a kerf width less than the diameter of the holes is employed to separate the individual devices. For accurate position alignment of repatterned die, an alignment structure, such as projecting pins or an egg crate structure, engages the die, and alignment pads can be patterned on the die.

Vaporization and deposition apparatus and process

Abstract: The invention relates to an apparatus and process for the vaporization of liquid precursors and deposition of a film on a suitable substrate. Particularly contemplated is an apparatus and process for the deposition of a metal-oxide film, such as a barium, strontium, titanium oxide (BST) film, on a silicon wafer to make integrated circuit capacitors useful in high capacity dynamic memory modules.

Apparatus and method for polishing a flat surface using a belted polishing pad

Abstract: The present invention relates to an apparatus and method of Chemical Mechanical Planarization ("CMP") for wafer, flat panel display (FPD), and hard drive disk (HDD). The preferred apparatus comprises a looped belt spatially oriented in a vertical direction with respect to a ground floor. A polishing pad is glued to an outer surface of the belt. At an inner surface of the belt, there are a plurality of wafer supports to support the wafers while they are in polishing process. Wafers are loaded from a wafer station to a wafer head using a handling structure before polishing and are unloaded from the wafer head to the wafer station after polishing. An electric motor or equivalent is used to drive the looped belt running over two pulleys. An adjustment means is used to adjust the tension and position of the belt for smooth running. This new CMP machine can be mounted in multiple orientations to save manufacturing space.

Effect of Surface Roughness on Room-Temperature Wafer Bonding by Ar Beam Surface Activation

Abstract: Using Ar beam etching in vacuum, strong bonding of Si wafers is attained at room temperature. With appropriate etching time, the bonding occurs spontaneously without any load to force two wafers together. However, surface roughness of the wafers increases during Ar beam etching. Because surface roughness has a strong influence on wafer bonding, long etching time degrades the bonding strength. Using atomic force microscope, we measured surface roughness enhancement caused by Ar beam etching, and investigated the relationship between surface roughness and bonding properties such as strength and interfacial voids. The results agree well with theoretical predictions using elastic theory and energy gain by bond formation. A guideline for successful room-temperature bonding is proposed from these results.

In situ plasma wafer bonding method

Abstract: A method for chemically bonding semiconductor wafers and other materials to one another without exposing wafers to wet environments, and a bonding chamber for in situ plasma bonding are disclosed. The in situ plasma bonding chamber allows plasma activation and bonding to occur without disruption of the vacuum level. This precludes rinsing of the surfaces after placement in the chamber, but allows for variations in ultimate pressure, plasma gas species, and backfill gases. The resulting bonded materials are free from macroscopic and microscopic voids. The initial bond is much stronger than conventional bonding techniques, thereby allowing for rougher materials to be bonded to one another. This bonded materials can be used for bond and etchback silicon on insulator, high voltage and current devices, radiation resistant devices, micromachined sensors and actuators, and hybrid semiconductor applications. This technique is not limited to semiconductors. Any material with sufficiently smooth surfaces that can withstand the vacuum and plasma environments may be bonded in this fashion.

Micromechanical accelerometer for automotive applications

Abstract: A micromechanical capacitive accelerometer is provided from a single silicon wafer. The basic structure of the micromechanical accelerometer is etched in the wafer to form a released portion in the substrate, and the released and remaining portions of the substrate are coated with metal under conditions sufficient to form a micromechanical capacitive accelerometer. The substrate is preferably etched using reactive-ion etching for at least the first etch step in the process that forms the basic structure, although in another preferred embodiment, all etching is reactive-ion etching. The accelerometer also may comprise a signal-conditioned accelerometer wherein signal-conditioning circuitry is provided on the same wafer from which the accelerometer is formed, and VLSI electronics may be integrated on the same wafer from which the accelerometer is formed. The micromechanical capacitive accelerometer can be used for airbag deployment, active suspension control, active steering control, anti-lock braking, and other control systems requiring accelerometers having high sensitivity, extreme accuracy and resistance to out of plane forces.

Method of processing wafers with low mass support

Abstract: A method is provided for treating wafers on a low mass support. The method includes mounting a temperature sensor in proximity to the wafer, which is supported on the low mass support, such that the sensor is only loosely thermally coupled to the wafer. A temperature controller is programmed to critically tune the wafer temperature in a temperature ramp, though the controller directly controls the sensor temperature. A wafer treatment, such as epitaxial silicon deposition, is started before the sensor temperature has stabilized. Accordingly, significant time is saved for the treatment process, and wafer throughput improved.