Showing papers on "Wafer published in 2002"

Synthesis of Large-Area Silicon Nanowire Arrays via Self-Assembling Nanoelectrochemistry

Abstract: Large-area silicon nanowire arrays have been prepared on a silicon wafer without the use of a template The simple method, which can be carried out near room temperature, involves the nanoelectrochemistry of silver nanowires in an aqueous HF solution containing silver nitrate This technique may be generally applicable to other semiconductors and metals The Figure shows nanodendritic silicon wires

Method of making a cutting instrument having integrated sensors

Abstract: A cutting instrument including a metal blade has a recess formed therein and a semiconductor substrate affixed to the blade in the recess. The semiconductor substrate includes at least one sensor formed thereon. The sensor formed on the semiconductor substrate may comprise at least one or an array of a strain sensors, pressure sensors, nerve sensors, temperature sensors, density sensors, accelerometers, and gyroscopes. The cutting instrument may also further include a handle wherein the blade is affixed to the handle and the semiconductor substrate is electrically coupled to the handle. The handle may then be coupled, either physically or by wireless transmission, to a computer that is adapted to display information to a person using the cutting instrument based on signals generated by one or more of the sensors formed on the semiconductor substrate. The computer or handle may also be adapted to store data based on the signals generated by one or more of the sensors. A method of making said cutting instrument includes the steps of at least one sensor being formed on a semiconductor wafer and a layer of photoresist being applied on a top side of the semiconductor wafer according to a pattern that matches the defined shape of the semiconductor substrate. The portion of the semiconductor wafer not covered by the photoresist is removed and thereafter the photoresist is removed from the semiconductor wafer, thereby leaving the semiconductor substrate having a defined shape and at least one sensor formed thereon. The semiconductor substrate having a defined shape and at least one sensor formed thereon is then affixed to a metal blade in a recess formed in said blade.

Chip and wafer integration process using vertical connections

Abstract: A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate. A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.

Molten gallium as a catalyst for the large-scale growth of highly aligned silica nanowires.

Abstract: The vapor-liquid-solid (VLS) process is a fundamental mechanism for the growth of nanowires, in which a small size (5-100 nm in diameter), high melting point metal (such as gold and iron) catalyst particle directs the nanowire's growth direction and defines the diameter of the crystalline nanowire. In this article, we show that the large size (5-50 Im in diameter), low melting point gallium droplets can be used as an effective catalyst for the large-scale growth of highly aligned, closely packed silica nanowire bunches. Unlike any previously observed results using gold or iron as catalyst, the gallium-catalyzed VLS growth exhibits many amazing growth phenomena. The silica nanowires tend to grow batch by batch. For each batch, numerous nanowires simultaneously nucleate, grow at nearly the same rate and direction, and simultaneously stop growing. The force between the batches periodically lifts the gallium catalyst upward, forming two different kinds of products on a silicon wafer and alumina substrate. On the silicon wafer, carrot-shaped tubes whose walls are composed of highly aligned silica nanowires with diameters of 15- 30 nm and length of 10-40 Im were obtained. On the alumina substrate, cometlike structures composed of highly oriented silica nanowires with diameters of 50-100 nm and length of 10-50 Im were formed. A growth model was proposed. The experimental results expand the VLS mechanism to a broader range.

Semiconductor device and method of manufacturing the same

Abstract: The method of manufacturing a semiconductor device of the present invention includes steps of; a resin layer forming process in which a face with electrodes of a semiconductor wafer having a plurality of semiconductor elements formed thereon is coated with a resin layer which has a function of sealing it; and a wafer thinning process in which the back face of the semiconductor wafer is ground. The method of manufacturing the semiconductor device of the present invention further includes a process of forming a conductive section on the electrodes of the semiconductor wafer with a plurality of semiconductor elements in such a manner the conductive section reaches to the electrodes. The manufacturing method of the semiconductor device of the present invention still further includes a process of cutting the semiconductor wafer having a plurality of semiconductor elements along boundaries of each semiconductor element. In the thinning process, at least one of a mechanical grinding method, a chemical etching method and a plasma etching method are employed.

Effect of process parameters on the surface morphology and mechanical performance of silicon structures after deep reactive ion etching (DRIE)

Abstract: The ability to predict and control the influence of process parameters during silicon etching is vital for the success of most MEMS devices. In the case of deep reactive ion etching (DRIE) of silicon substrates, experimental results indicate that etch performance as well as surface morphology and post-etch mechanical behavior have a strong dependence on processing parameters. In order to understand the influence of these parameters, a set of experiments was designed and performed to fully characterize the sensitivity of surface morphology and mechanical behavior of silicon samples produced with different DRIE operating conditions. The designed experiment involved a matrix of 55 silicon wafers with radius hub flexure (RHF) specimens which were etched 10 min under varying DRIE processing conditions. Data collected by interferometry, atomic force microscopy (AFM), profilometry, and scanning electron microscopy (SEM), was used to determine the response of etching performance to operating conditions. The data collected for fracture strength was analyzed and modeled by finite element computation. The data was then fitted to response surfaces to model the dependence of response variables on dry processing conditions.

Guidelines for etching silicon MEMS structures using fluorine high-density plasmas at cryogenic temperatures

Abstract: This paper presents guidelines for the deep reactive ion etching (DRIE) of silicon MEMS structures, employing SF/sub 6//O/sub 2/-based high-density plasmas at cryogenic temperatures. Procedures of how to tune the equipment for optimal results with respect to etch rate and profile control are described. Profile control is a delicate balance between the respective etching and deposition rates of a SiO/sub x/F/sub y/ passivation layer on the sidewalls and bottom of an etched structure in relation to the silicon removal rate from unpassivated areas. Any parameter that affects the relative rates of these processes has an effect on profile control. The deposition of the SiO/sub x/F/sub y/ layer is mainly determined by the oxygen content in the SF/sub 6/ gas flow and the electrode temperature. Removal of the SiO/sub x/F/sub y/ layer is mainly determined by the kinetic energy (self-bias) of ions in the SF/sub 6//O/sub 2/ plasma. Diagrams for profile control are given as a function of parameter settings, employing the previously published "black silicon method". Parameter settings for high rate silicon bulk etching, and the etching of micro needles and micro moulds are discussed, which demonstrate the usefulness of the diagrams for optimal design of etched features. Furthermore, it is demonstrated that in order to use the oxygen flow as a control parameter for cryogenic DRIE, it is necessary to avoid or at least restrict the presence of fused silica as a dome material, because this material may release oxygen due to corrosion during operation of the plasma source. When inert dome materials like alumina are used, etching recipes can be defined for a broad variety of microstructures in the cryogenic temperature regime. Recipes with relatively low oxygen content (1-10% of the total gas volume) and ions with low kinetic energy can now be applied to observe a low lateral etch rate beneath the mask, and a high selectivity (more than 500) of silicon etching with respect to polymers and oxide mask materials is obtained. Crystallographic preference etching of silicon is observed at low wafer temperature (-120/spl deg/C). This effect is enhanced by increasing the process pressure above 10 mtorr or for low ion energies (below 20 eV).

Method and apparatus for electro-chemical mechanical deposition

Abstract: The present invention deposits a conductive material from an electrolyte solution to a predetermined area of a wafer. The steps that are used when making this application include applying the conductive material to the predetermined area of the wafer using an electrolyte solution disposed on a surface of the wafer, when the wafer is disposed between a cathode and an anode, and preventing accumulation of the conductive material to areas other than the predetermine area by mechanically polishing the other areas while the conductive material is being applied.

Very low bulk and surface recombination in oxidized silicon wafers

Abstract: Bulk and surface processes determine the recombination rate in crystalline silicon wafers. In this paper we report effective lifetime measurements for a variety of commercially available float-zone silicon wafers that have been carefully passivated using alnealed silicon oxide. Different substrate resistivities have been explored, including both p-type (boron) and n-type (phosphorus) dopants. Record high effective lifetimes of 29 and 32 ms have been measured for 90 Ω cm n-type and 150 Ω cm p-type silicon wafers, respectively. The dependence of the effective lifetime has been measured for excess carrier densities in the range of 1012–1017 cm−3. These results demonstrate that very low bulk and surface recombination rates can be maintained during high-temperature oxidation (1050 °C) by carefully optimizing the processing conditions.

System and method for forming a gate dielectric

Abstract: A method of forming a dielectric stack on a pre-treated surface. The method comprises pre-cleaning a semiconductor wafer to remove native oxide, such as by applying hydroflouric acid to form an HF-last surface, pre-treating the HF-last surface with ozonated deionized water, forming a dielectric stack on the pre-treated surface and providing a flow of NH3 in a process zone surrounding the wafer. Alternately, the method includes pre-treating the HF-last surface with NH3, forming the stack after the pre-treating, and providing a flow of N2 in a process zone surrounding the wafer after the forming. The method also includes pre-treating the HF-last surface using an in-situ steam generation process, forming the stack on the pre-treated surface, and annealing the wafer after the forming. The pre-treating includes providing an inert gas flow in a process zone surrounding the HF-last surface, reacting hydrogen with an oxidizer in the process zone for a very short duration, and providing an inert gas flew in the process zone after the reacting.

Three-dimensional integrated semiconductor devices

Abstract: The present invention describes a process for three-dimensional integration of semiconductor devices and a resulting device. The process combines low temperature wafer bonding methods with backside/substrate contact processing methods, preferably with silicon on insulator devices. The present invention utilizes, in an inventive fashion, low temperature bonding processes used for bonded silicon on insulator (SOI) wafer technology. This low temperature bonding technology is adopted for stacking several silicon layers on top of each other and building active transistors and other circuit elements in each one. The back-side/substrate contact processing methods allow the interconnection of the bonded SOI layers.

Wafer level stack chip package and method for manufacturing same

Abstract: A wafer level chip package has a redistrubution substrate, at least one lower semiconductor chip stacked on the redisctribution substrate, and an uppermost semiconductor chip. The redistribution substrate has a redistribution layer and substrate pads connected to the redistribution layer. The lower semiconductor chip is stacked on the redistribution layer and may have through holes for partially exposing the redistribution layer, the through holes corresponding to the substrate pads, and having conductive filling material filling the through holes. The uppermost semiconductor chip may have the same elements as the lower semiconductor chip, and may be flip chip bonded to the through holes. The package may further have a filling layer for filling areas between chips, a metal lid for coating most of the external surfaces, and external connection terminals formed on and electrically connected to the exposed redistribution layer from the first dielectric layer of the redistribution substrate.

Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack

Abstract: A three-dimensional (3-D) integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices, metallic lines deposited via an interlevel dielectric (ILD) on a surface, and at least one barrier line deposited on an outer edge of the surface; and a second wafer including one or more integrated circuit (IC) devices, metallic lines deposited via an interlevel dielectric (ILD) on a surface, and at least one barrier line deposited on an outer edge of the surface, wherein the metallic lines and the barrier line deposited on the surface of the second wafer are bonded with the metallic lines and the barrier line deposited on the surface of the first wafer to establish electrical connections between active IC devices on adjacent wafers and to form a barrier structure on the outer edge of the adjacent wafers.

H2S sensing properties of noble metal doped WO3 thin film sensor fabricated by micromachining

Abstract: The purpose of this research is to develop a semiconductor-type H2S gas sensor with silicon-based microfabrication and micromachining technology. This successful approach allows for the production of small, geometrically well-defined sensors that are reliable and mechanically robust, and is compatible with VLSI processes. Individual sensor cost is also greatly reduced because the sensors are batch fabricated. The main sensing region is covered with a 300 μm ×300 μm WO3 thin film, which is deposited by RF sputtering on silicon wafer substrate. Platinum (Pt), gold (Au) or Au-Pt noble metals was then deposited onto WO3 thin film as activator layer by sputtering. Under 1 ppm H2S and at an operating temperature of 220 °C, the individual sensitivities of the Pt and the Au-Pt doped WO3 gas sensors are 23 and 5.5, respectively. The sensor response times of Pt, Au-Pt and Au doped WO3 thin films are 30, 2 and 8 s, respectively, and the recovery times are about 30, 30 and 160 s, respectively. The results show that the Pt doped WO3 gas sensor exhibits acceptable response time, recovery time and as well as a high sensitivity.

Semiconductor wafer edge marking

Abstract: The marking of identification and orientation information along the edge (E) of a semiconductor wafer (20, 20′) is disclosed. The information may be marked by way of laser marking at one or more locations (10) along a flat portion (14) or bevel (12 t , 12 b) of the edge (E) of the wafer (20, 20′). The wafer marking (10) may be encoded, for example by way of a 2-D bar code. A system (30) for reading the identification information from wafers (20, 20′) in a carrier (32) is also disclosed. The system (30) includes a sensor (36) for sensing reflected light from the wafer markings (10) along the wafer edge (E), and for decoding identification and orientation therefrom. A motor (38), under the control of feedback (RFB) from the sensor (36), rotates the wafers (20, 20′) by way of a roller (39) until the wafer marking (10) is in view by the sensor (36). A processing system (40), which includes a rotatable chuck (41) upon which the wafer (20, 20′) is placed, is also disclosed. The processing system (40) also includes a sensor (36) for sensing identification and orientation information from the wafer edge (E), and a process control computer (46) that receives signals corresponding to the identification information, for purposes of manufacturing data logging and process control.

Semiconductor device and its manufacture method

Abstract: A semiconductor device formed by cutting a first substrate and a second substrate bonded together by a spacer, wherein: the spacer is disposed at an end of the first substrate after cutting; the second substrate is a semiconductor wafer formed with a light reception element or elements; and the first substrate has an optical element or an optical element set for converging light on the light reception element or elements. A method of manufacturing such a semiconductor device. A semiconductor device manufacture method includes: a step of detecting a warp of a semiconductor substrate; a step of holding the semiconductor substrate on a base under a condition that the warp is removed; a step of bonding an opposing substrate to the semiconductor substrate; and a step of cutting the opposing substrate, wherein the opposing substrate bonded to the semiconductor substrate is set with a size corresponding to the warp of the semiconductor substrate or with a gap to an adjacent opposing substrate.

Dynamic etching of silicon for broadband antireflection applications

Abstract: An electrochemical etching technique has been developed that provides continuous control over the porosity of a porous silicon layer as a function of etching depth. Thin films with engineered porosity gradients, and thus a controllable gradient in the index of refraction, have been used to demonstrate broadband antireflection properties on silicon wafer and solar cell substrates. A simulation was also developed to examine the effects of specific porosity profiles on film reflectivity.

Hermetically sealed microstructure package

Abstract: A hermetically sealed wafer scale package for micro-electrical-mechanical systems devices. The package consists of a substrate wafer which contains a microstructure and a cap wafer which contains other circuitry and electrical connectors to connect to external applications. The wafers are bonded together, and the microstructure sealed, with a sealant, which in the preferred embodiment is frit glass. The wafers are electrically connected by a wire bond, which is protected by an overmold. Electrical connectors are applied to the cap wafer, which are electrically linked to the outputs and inputs of the microstructure. The final package is small, easy to manufacture and test, and more cost efficient than current hermetically sealed microstructure packages.

High surface quality gan wafer and method of fabricating same

Abstract: A high quality wafer comprising AlxGayInzN, wherein 0

Method of forming overmolded chip scale package and resulting product

Abstract: A method for forming a semiconductor device includes forming a conductive bump on one or more of bond pads of a semiconductor substrate of a semiconductor wafer. A top or uppermost portion of each conductive bump is then planarized. The exposed portions of an active surface of the semiconductor wafer are filled with a layer of encapsulation material. The conductive bumps are reformed to their preplanarized shape and the semiconductor wafer is then diced to form singulated semiconductor dice. A preferred method of the invention also includes placing each singulated die in a mold to complete a second encapsulation step wherein a layer of encapsulation material is formed on the back surface or, alternatively, on the back and side surfaces of the semiconductor die in order to encapsulate the back, or the back and sides, of the semiconductor die.

Stackable semiconductor package and wafer level fabrication method

Abstract: A stackable semiconductor package includes a semiconductor die, and has a chip sized peripheral outline matching that of the die. In addition to the die, the package includes stacking pads and stacking contacts on opposing sides of the die, and conductive grooves on the edges of the die in electrical communication with the stacking pads and the stacking contacts. The conductive grooves function as interlevel conductors for the package and can also function as edge contacts for the package. The configuration of the stacking pads, of the stacking contacts and of the conductive grooves permit multiple packages to be stacked and electrically interconnected to form stacked assemblies. A method for fabricating the package is performed at the wafer level on a substrate, such as a semiconductor wafer, containing multiple dice. In addition, multiple substrates can be stacked, bonded and singulated to form stacked assemblies that include multiple stacked packages.

Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same

Abstract: A three-dimensional (3-D) integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices; a second wafer including one or more integrated circuit (IC) devices; and metallic lines deposited on opposing surfaces of the first and second wafers at designated locations with an interlevel dielectric (ILD) recess surrounding the metallic lines to facilitate direct metal bonding between the first and second wafers and establish electrical connections between active IC devices on the first and second wafers.

A surface-tension driven micropump for low-voltage and low-power operations

Abstract: In this paper, we first report a micropump actuated by surface tension based on continuous electrowetting (CEW). We have used the surface-tension-induced motion of a mercury drop in a microchannel filled with an electrolyte as actuation energy for the micropump. This allows low voltage operation as well as low-power consumption. The micropump is composed of a stack of three wafers bonded together. The microchannel is formed on a glass wafer using SU-8 and is filled with electrolyte where the mercury drop is inserted. The movement of the mercury pushes or drags the electrolyte, resulting in the deflection of a membrane that is formed on the second silicon wafer. Another silicon wafer, which has passive check valves and holes, is stacked on the membrane wafer, forming inlet and outlet chambers. Finally, these two chambers are connected through a silicone tube forming the complete micropump. The performance of the fabricated micropump has been tested for various operation voltages and frequencies. We have demonstrated actual liquid pumping up to 70 /spl mu/l/min with a driving voltage of 2.3 V and a power consumption of 170 /spl mu/W. The maximum pump pressure is about 800 Pa at the applied voltage of 2.3 V with an operation frequency of 25 Hz.

Tandem wafer processing system and process

Abstract: The present invention generally provides a cassette-to-cassette vacuum processing system which concurrently processes multiple wafers and combines the advantages of single wafer process chambers and multiple wafer handling for high quality wafer processing, high wafer throughput and reduced footprint. In accordance with one aspect of the invention, the system is preferably a staged vacuum system which generally includes a loadlock chamber for introducing wafers into the system and which also provides wafer cooling following processing, a transfer chamber for housing a wafer handler, and one or more processing chambers each having two or more processing regions which are isolatable from each other and preferably share a common gas supply and a common exhaust pump. The processing regions also preferably include separate gas distribution assemblies and RF power sources to provide a uniform plasma density over a wafer surface in each processing region. The processing chambers are configured to allow multiple, isolated processes to be performed concurrently in at least two processing regions so that at least two wafers can be processed simultaneously in a chamber with a high degree of process control.

Fabrication of semiconductor interconnect structures

Abstract: A system and a method of forming copper interconnect structures in a surface of a wafer is provided. The method includes a step of performing a planar electroplating process in an electrochemical mechanical deposition station for filling copper material into a plurality of cavities formed in the surface of the wafer. The electroplating continues until a planar layer of copper with a predetermined thickness is formed on the surface of the wafer. In a following chemical mechanical polishing step the planar layer is removed until the copper remains in the cavities, insulated from one another by exposed regions of the dielectric layer.

Semiconductor processing apparatus comprising chamber partitioned into reaction and transfer sections

Abstract: Semiconductor processing equipment that has increased efficiency, throughput, and stability, as well as reduced operating cost, footprint, and faceprint is provided Other than during deposition, the atmosphere of both the reaction chamber and the transfer chamber are evacuated using the transfer chamber exhaust port, which is located below the surface of the semiconductor wafer This configuration prevents particles generated during wafer transfer or during deposition from adhering to the surface of the semiconductor wafer Additionally, by introducing a purge gas into the transfer chamber during deposition, and by using an insulation separating plate 34, the atmospheres of the transfer and reaction chambers can be effectively isolated from each other, thereby preventing deposition on the walls and components of the transfer chamber Finally, the configuration described herein permits a wafer buffer mechanism to be used with the semiconductor processing equipment, thereby further increasing throughput and efficiency

Synthesis of Ultra‐Long and Highly Oriented Silicon Oxide Nanowires from Liquid Alloys

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Interlocking conductor method for bonding wafers to produce stacked integrated circuits

Abstract: An integrated circuit wafer element and an improved method for bonding the same to produce a stacked integrated circuit. Plugs that extend from one surface of the wafer into the wafer are used to provide vertical connections and to bond the wafers together. A stacked integrated circuit is constructed by bonding the front side of a new wafer to a wafer in the stack and then thinning the backside of the new wafer to a thickness that leaves a portion of the plugs extending above the surface of the backside of the thinned wafer. The elevated plug ends can then be used to bond another wafer by bonding to pads on the front side of that wafer. The mating bonding pads can include depressed regions that mate to the elevated plug ends.

Method and apparatus for micro-jet enabled, low-energy ion generation and transport in plasma processing

Abstract: A method for creating and transporting low-energy ions for use in plasma processing of a semiconductor wafer is disclosed. In an exemplary embodiment of the invention, the method includes generating plasma from a gas species to produce a plasma exhaust. The plasma exhaust is then introduced into a processing chamber containing the wafer. The ion content of the plasma exhaust is enhanced by activating a supplemental ion source as the plasma is introduced into the processing chamber, thereby creating a primary plasma discharge therein. Then, the primary plasma discharge is directed into a baffle plate assembly, thereby creating a secondary plasma discharge exiting the baffle plate assembly. The strength of an electric field exerted on ions contained in the secondary plasma discharge is reduced. In so doing, the reduced strength of the electric field causes the ions to bombard the wafer at an energy insufficient to cause damage to semiconductor devices formed on the wafer.

Semiconductor wafer having a thin die and tethers and methods of making the same

Abstract: A semiconductor wafer ( 70 ) that includes a support body ( 72 ), at least one thin die ( 20, 60 ), and a plurality of tethers ( 78, 178 ). The support body ( 72 ) is made of a semiconductor material. The thin die ( 20, 60 ) has a circuit ( 21 ) formed thereon and has an outer perimeter ( 74 ) defined by an open trench ( 76 ). The open trench ( 76 ) separates the thin die ( 20, 60 ) from the support body ( 72 ). The tethers ( 78, 178 ) extend across the open trench ( 76 ) and between the support body ( 72 ) and the thin die ( 20, 60 ). A method of making a thin die ( 20, 60 ) on a wafer ( 70 ) where the wafer ( 70 ) has a support body ( 72 ), a topside ( 82 ) and a backside ( 90 ). A circuit ( 21 ) is formed on the topside ( 82 ) of the wafer ( 70 ). The method may include the steps of: forming a cavity ( 88 ) on the backside ( 90 ) of the wafer ( 70 ) beneath the circuit ( 21 ) that defines a first layer ( 92 ) that includes the circuit ( 21 ); forming a trench ( 76 ) around the circuit ( 21 ) on the topside ( 82 ) of the wafer ( 70 ) that defines an outer perimeter ( 74 ) of the thin die ( 20, 60 ); forming a plurality of tethers ( 78, 178 ) that extend across the trench ( 76 ) and between the wafer support body ( 72 ) and the thin die ( 20, 60 ); and removing a portion of the first layer ( 92 ) to define the bottom surface ( 75 ) of the thin die ( 20, 60 ).