Showing papers on "Wafer published in 2004"

Large-scale fabrication of wafer-size colloidal crystals, macroporous polymers and nanocomposites by spin-coating.

Abstract: This paper reports a simple spin-coating technique for rapidly fabricating three types of technologically important materials--colloidal crystal, macroporous polymer, and polymeric nanocomposite, each with high crystalline qualities and wafer-scale sizes. Dispersion of monodisperse silica colloids in triacrylate monomers is spin-coated onto a variety of substrates. Shear-induced ordering and subsequent polymerization lead to the formation of three-dimensionally (3D) ordered colloidal crystals trapped inside a polymer matrix. The thickness of as-synthesized colloidal crystal-polymer nanocomposite is highly uniform and can be controlled simply by changing the spin speed and time. Selective removal of the polymer matrix and silica spheres lead to the formation of large-area colloidal crystals and macroporous polymers, respectively. The wafer-scale process is compatible with standard semiconductor microfabrication, as multiple micrometer-sized patterns can be created simultaneously for potential device applications. Normal-incidence transmission spectra in the visible and near-infrared regions show distinct peaks due to Bragg diffraction from 3D ordered structures. The spin-coating process opens a new route to the fundamental studies of shear-induced crystallization, melting and relaxation.

A three-dimensional optical photonic crystal with designed point defects.

Abstract: Photonic crystals1,2,3 offer unprecedented opportunities for miniaturization and integration of optical devices. They also exhibit a variety of new physical phenomena, including suppression or enhancement of spontaneous emission, low-threshold lasing, and quantum information processing4. Various techniques for the fabrication of three-dimensional (3D) photonic crystals—such as silicon micromachining5, wafer fusion bonding6, holographic lithography7, self-assembly8,9, angled-etching10, micromanipulation11, glancing-angle deposition12 and auto-cloning13,14—have been proposed and demonstrated with different levels of success. However, a critical step towards the fabrication of functional 3D devices, that is, the incorporation of microcavities or waveguides in a controllable way, has not been achieved at optical wavelengths. Here we present the fabrication of 3D photonic crystals that are particularly suited for optical device integration using a lithographic layer-by-layer approach15. Point-defect microcavities are introduced during the fabrication process and optical measurements show they have resonant signatures around telecommunications wavelengths (1.3–1.5 µm). Measurements of reflectance and transmittance at near-infrared are in good agreement with numerical simulations.

A printable form of silicon for high performance thin film transistors on plastic substrates

Abstract: Free-standing micro- and nanoscale objects of single crystal silicon can be fabricated from silicon-on-insulator wafers by lithographic patterning of resist, etching of the exposed top silicon, and removing the underlying SiO2 to lift-off the remaining silicon. A large collection of such objects constitutes a type of material that can be deposited and patterned, by dry transfer printing or solution casting, onto plastic substrates to yield mechanically flexible thin film transistors that have excellent electrical properties. Effective mobilities of devices built with this material, which we refer to as microstructured silicon (μs-Si), are demonstrated to be as high as 180cm2∕Vs on plastic substrates. This form of “top down” microtechnology might represent an attractive route to high performance flexible electronic systems.

Microchip fabrication : a practical guide to semiconductor processing

Abstract: The Semiconductor Industry International Technology Roadmap for Semiconductors Semiconductor Materials and Process Chemicals Manufacturing Wafers Overview of Wafer Fabrication 300mm wafer diameter processing Contamination Control Process Yields Nanotechnology Processes Oxidation Basic Patterning -- Surface Preparation to Exposure Basic Patterning -- Developing to Final Inspection Advanced Photolithography Processes Doping Deposition of Dielectrics and Semiconductor Layers Metalization: Wiring the Chip Composites Process and Device Evaluation The Business of Water Fabrication Green Processing Semiconductor Devices and Integrated Circuit Formation Nanotechnology Devices Integrated Circuit Types Packaging GLOSSARY

Led power package

Abstract: Surface mount light emitting diode (LED) packages each contain a light emitting diode (LED) die (24). A plurality of arrays of openings are drilled into an electrically insulating sub-mount wafer (10). A metal is applied to the drilled openings to produce a plurality of via arrays (12). The LED dice (24) are flip-chip bonded onto a frontside (16) of the sub-mount wafer (10). The p-type and n-type contacts of each flip-chip bonded LED (24) electrically communicate with a solderable backside (18) of the sub-mount wafer (10) through a via array (12). A thermal conduction path (10, 12) is provided for thermally conducting heat from the flip-chip bonded LED dice (24) to the solderable backside (18) of the sub­mount wafer (10). Subsequent to the flip-chip bonding, the sub-mount wafer (10) is separated to produce the surface mount LED packages.

Fet channel having a strained lattice structure along multiple surfaces

Abstract: A channel (16) of a FinFET (10) has a channel core (24) and a channel envelope (32), each made from a semiconductor material defining a different lattice structure to exploit strained silicon properties. A gate is coupled to the channel envelope through a gate dielectric. Exemplary materials are Si and SixGe1-x, wherein 78

Metal–insulator–semiconductor optoelectronic fibres

Abstract: The combination of conductors, semiconductors and insulators with well-defined geometries and at prescribed length scales, while forming intimate interfaces, is essential in most functional electronic and optoelectronic devices. These are typically produced using a variety of elaborate wafer-based processes, which allow for small features, but are restricted to planar geometries and limited coverage area1,2,3. In contrast, the technique of fibre drawing from a preformed reel or tube is simpler and yields extended lengths of highly uniform fibres with well-controlled geometries and good optical transport characteristics4. So far, this technique has been restricted to particular materials5,6,7 and larger features8,9,10,11,12. Here we report on the design, fabrication and characterization of fibres made of conducting, semiconducting and insulating materials in intimate contact and in a variety of geometries. We demonstrate that this approach can be used to construct a tunable fibre photodetector comprising an amorphous semiconductor core contacted by metallic microwires, and surrounded by a cylindrical-shell resonant optical cavity. Such a fibre is sensitive to illumination along its entire length (tens of meters), thus forming a photodetecting element of dimensionality one. We also construct a grid of such fibres that can identify the location of an illumination point. The advantage of this type of photodetector array is that it needs a number of elements of only order N, in contrast to the conventional order N2 for detector arrays made of photodetecting elements of dimensionality zero.

Fabricating semiconductor nano/microwires and transfer printing ordered arrays of them onto plastic substrates

Abstract: Ordered arrays of single-crystalline nano- and microwires of GaAs and InP with well-controlled lengths, widths, and cross-sectional shapes have been fabricated over large areas from high quality bulk wafers by the use of traditional photolithography and anisotropic, chemical wet etching. A printing technique using elastomeric stamps can transfer these wire arrays to plastic substrates, with excellent retention of order and crystallographic orientation of the wires. Electrical measurements on simple test structures demonstrate the high degree of mechanical flexibility of the resulting wire arrays on plastics. The combination of “top down” wire fabrication and “dry” transfer printing might represent an effective route to ultrahigh performance macroelectronic systems.

Method of fabrication of stacked semiconductor devices

Abstract: A method for increasing integrated circuit density is disclosed comprising stacking an upper wafer and a lower wafer, each of which having fabricated circuitry in specific areas on their respective face surfaces. The upper wafer is attached back-to-back with the lower wafer with a layer of adhesive applied over the back side of the lower wafer. The wafers are aligned so as to bring complementary circuitry on each of the wafers into perpendicular alignment. The adhered wafer pair is then itself attached to an adhesive film to immobilize the wafer during dicing. The adhered wafer pair may be diced into individual die pairs or wafer portions containing more than one die pair.

High-power dielectric seasoning for stable wafer-to-wafer thickness uniformity of dielectric cvd films

Abstract: A method for seasoning a deposition chamber wherein the chamber components and walls are densely coated with a material that does not contain carbon prior to deposition of an organo-silicon material on a substrate. An optional carbon-containing layer may be deposited therebetween. A chamber cleaning method using low energy plasma and low pressure to remove residue from internal chamber surfaces is provided and may be combined with the seasoning process.

Apparatus and method for surface cleaning using plasma

Abstract: There is provided a surface cleaning apparatus and method using plasma to remove a native oxide layer, a chemical oxide layer, and a damaged portion from a silicon substrate surface, and contaminants from a metal surface. By absorbing potential in a grounded grid or baffle between a plasma generator and a substrate, only radicals are passed to the substrate, and HF gas is used as a second processing gas. Thus a native oxide layer, a chemical oxide layer, or a damaged portion formed on the silicon substrate during etching a contact hole is removed and the environment of a chamber is maintained constant by introducing a conditioning gas after each wafer process. Therefore, process uniformity is improved.

Transferable device-containing layer for silicon-on-insulator applications

Abstract: A method for forming an integrated circuit on an insulating substrate is described comprising the steps of forming a semiconductor layer on a seed wafer substrate containing an at least partially crystalline porous release layer, processing the semiconductor layer to form a “transferable” device layer containing at least one semiconductor device, and bonding said transferable device layer to a final, insulating substrate before or after separating said device layer from the seed wafer substrate. A second method, for separating a semiconductor layer from a seed wafer substrate, is described wherein an at least partially crystalline porous layer initially connecting the semiconductor layer and seed wafer substrate is split or broken apart by the steps of (i) introducing a fluid including water into the pores of said porous layer, and (ii) expanding said fluid by solidifying or freezing to break apart the porous layer. The at least partially crystalline porous layer may incorporate at least one porous silicon germanium alloy layer alone or in combination with at least one porous Si layer. Also described is an integrated circuit comprising the transfered device layer described above.

Novel three-dimensional embedded SU-8 microchannels fabricated using a low temperature full wafer adhesive bonding

Abstract: This paper describes a novel fabrication method for the manufacture of three-dimensional (3D) interconnected microchannels. The fabrication is based on a full wafer polymer bonding process, using SU-8 polymer epoxy photoresist as a structural material. The technology development includes an improvement of the SU-8 photolithography process in order to produce high uniformity films with good adhesive properties. Hence, 3D embedded microchannels are fabricated by a low temperature adhesive bonding of the SU-8 photopatterned thick films. The bonding occurs at temperatures (100–120 °C) lower than those usually applied in bonding technology. The bonding process parameters have been chosen in order to achieve a strong and void-free bond. High bond strengths, up to 8 MPa, have been obtained. Several examples using this new technology are shown, including bonding between different combinations of silicon and Pyrex wafers. This method also allows us to bond wafers with previously surface micromachined structures. Interconnected microchannels with vertical smooth walls and aspect ratios up to five have been obtained. Channels from 40 to 60 µm depth and from 10 to 250 µm width have been achieved. Liquid has been introduced at different levels into the microchannels, verifying good sealing of the 3D interconnected microchannels. The fabrication procedure described in this paper is fast, reproducible, CMOS compatible and easily implementable using standard photolithography and bonding equipment.

Vacuum package fabrication of integrated circuit components

Abstract: A method for manufacturing integrated circuit device lids includes creating a lid cavity on the surface of a lid wafer, forming a sealing surface on the lid wafer that surrounds the lid cavity, and forming a trench on the lid wafer between the lid cavity and the sealing surface. The resulting structure uptakes excess sealing surface material and prevents such material from entering the lid cavity.

Study of GaN light-emitting diodes fabricated by laser lift-off technique

Abstract: The fabrication process and performance characteristics of the laser lift-off (LLO) GaN light-emitting diodes (LEDs) were investigated. The LLO-GaN LEDs were fabricated by lifting off the GaN LED wafer structure grown on the original sapphire substrate by a KrF excimer laser at 248 nm wavelength with the laser fluence of 0.6 J/cm2 and transferring it onto a Cu substrate. The LLO-GaN LEDs on Cu show a nearly four-fold increase in the light output power over the regular LLO-LEDs on the sapphire substrate. High operation current up to 400 mA for the LLO-LEDs on Cu was also demonstrated. Based on the emission wavelength shift with the operating current data, the LLO-LEDs on Cu show an estimated improvement of heat dissipation capacities by nearly four times over the light-emitting devices on sapphire substrate. The LLO process should be applicable to other GaN-based LEDs in particular for those high light output power and high operation current devices.

Method and structure to improve reliability of copper interconnects

Abstract: A method of forming a conductor structure on a surface of a wafer is provided. The surface of the wafer includes cavities separated by field regions. Initially, a barrier layer is deposited on the surface that includes cavities separated by field regions. A thin seed layer with a substantially uniform thickness is deposited on the barrier layer. The barrier layer and the seed layer portions in the cavities occupy less than 30% of the volume of each cavity. The remaining volume of each cavity is filled with a conductive material which is formed on the seed layer. The conductive layer has a substantially small thickness. After forming the conductive layer, the wafer is annealed to increase grain size in the conductive layer and the seed layer.

System and method of fabricating micro cavities

Abstract: A system and method for manufacturing micro cavities at the wafer level using a unique, innovative MEMS (MicroElectroMechanical Systems) process, wherein micro cavities are formed, with epoxy bonded single-crystalline silicon membrane as cap and deposited and/or electroplated metal as sidewall, on substrate wafers. The epoxy is also the sacrificial layer. It is totally removed from within the cavity through small etch access holes etched in the silicon cap before the etch access holes are sealed under vacuum. The micro cavities manufactured therein can be used as pressure sensors or for packaging MEMS devices under vacuum or inert environment. In addition, the silicon membrane manufactured therein can be used to manufacture RF switches.

Immersion photolithography system and method using inverted wafer-projection optics interface

Abstract: A liquid immersion photolithography system includes an exposure system that exposes a substrate with electromagnetic radiation, and also includes a projection optical system that focuses the electromagnetic radiation on the substrate. A liquid supply system provides a liquid between the projection optical system and the substrate. The projection optical system is positioned below the substrate.

Wafer Support Tool for Heat Treatment and Heat Treatment Apparatus

Abstract: The present invention provides a wafer support tool for heat treatment easy in working and capable of realizing reduction in cost without generating damages or slip dislocations that would be otherwise caused by high temperature heat treatment and a heat treatment apparatus. The present invention is directed to a wafer support tool for heat treatment comprising: a plurality of wafer support members for supporting a wafer to be heat treated; and a support member holder for holding the wafer support members, wherein the wafer support members each has a contact portion with the wafer, at least one of the contact portions being movable relative to the support member holder.

Method of removing oxide layer and semiconductor manufacturing apparatus for removing oxide layer

Abstract: A method for removing an oxide layer such as a natural oxide layer and a semiconductor manufacturing apparatus which uses the method to remove the oxide layer. A vertically movable susceptor is installed at the lower portion in a processing chamber and a silicon wafer is loaded onto the susceptor when it is at the lower portion of the processing chamber. The air is exhausted from the processing chamber to form a vacuum condition therein. A hydrogen gas in a plasma state and a fluorine-containing gas are supplied into the processing chamber to induce a chemical reaction with the oxide layer on the silicon wafer, resulting in a reaction layer. Then, the susceptor is moved up to the upper portion of the processing chamber, to anneal the silicon wafer on the susceptor with a heater installed at the upper portion of the processing chamber, thus vaporizing the reaction layer. The vaporized reaction layer is exhausted out of the chamber. The oxide layer can be removed with a high selectivity while avoiding damage or contamination of the underlying layer.

Semiconductor manufacturing system and wafer holder for semiconductor manufacturing system

Abstract: A semiconductor manufacturing system and wafer holder for a semiconductor manufacturing system which prevents a semiconductor wafer from being exposed to a process reaction and which includes a reaction tube for providing a sealed process space and a dual boat and which prevents the backside deposition by the wafer holder. The wafer holder includes a holder body to hide the backside of the semiconductor wafer during a process in the reaction tube and a wafer lifter having a portion that can be disengaged from and coupled to the holder body so that a lower portion of the semiconductor wafer is supported by the dual boat and so that the semiconductor wafer can be lifted up from the wafer body when the semiconductor wafer is loaded and unloaded. A separation boundary between the holder body and the wafer lifter includes a gas inflow interception surface to hinder reaction gas from flowing through the separation boundary.

A new masking technology for deep glass etching and its microfluidic application

Abstract: A new masking technology for wet etching of glass, to a depth of more than 300µm, is reported Various mask materials, which can be patterned by standard photolithography and metal etching processes, were investigated for glass etching in concentrated hydrofluoric acid (HF) A multilayer of metal, Cr/Au/Cr/Au, in combination with thick SPR220-7 photoresist, was found to be ideal for this purpose Through holes etched from both sides of a 500µm thick Pyrex glass wafer were obtained Pinholes, created in the glass by failure of simple metal masking when subjected to HF etching, were successfully eliminated using the new masking technology In addition, the lateral undercutting of glass caused by the under-etching of the Cr mask was minimized to 27% of the etching depth With these advantages, this newly developed masking method was successfully applied to fabricate microfluidic components for a micro-peristaltic pump to be integrated in a micro polymerase chain reaction (PCR) device These components include through holes for liquid accessing and electrical contacting and a 200µm thick pump diaphragm This new masking technology also adds to the methods available to fabricate the microfluidic devices in glass substrates

Pass through via technology for use during the manufacture of a semiconductor device

Abstract: A method for forming vias which pass through a semiconductor wafer substrate assembly such as a semiconductor die or wafer allows two different types of connections to be formed during a single formation process. One connection passes through the wafer without being electrically coupled to the wafer, while the other connection electrically connects to a conductive pad. To connect to a pad, a larger opening is etched into an overlying dielectric layer, while to pass through a pad without connection, a narrower opening is etched into the overlying dielectric layer. An inventive structure resulting from the method is also described.

Glass frit bonding : An universal technology for wafer level encapsulation and packaging

Abstract: This paper reports on glass frit wafer bonding, which is a universally usable technology for wafer level encapsulation and packaging. After explaining the principle and the process flow of glass frit bonding, experimental results are shown. Glass frit bonding technology enables bonding of surface materials commonly used in MEMS technology. It allows hermetic sealing and a high process yield. Metal lead throughs at the bond interface are possible, because of the planarizing glass interlayer. Examples of surface micromachined sensors demonstrate the potential of glass-frit bonding.

Wafer bonding using microwave heating of parylene intermediate layers

Abstract: This paper describes a novel wafer bonding technique using microwave heating of parylene intermediate layers. The bonding is achieved by parylene deposition and thermal lamination using microwave heating. Variable frequency microwave heating provides uniform, selective and rapid heating for parylene intermediate layers. The advantages of this bonding technique include short bonding time, low bonding temperature, relatively high bonding strength, less void generation and low thermal stress. In addition, the intermediate layer material, parylene, is chemically stable and biocompatible. This bonding technique can be used for structured wafers also because parylene provides a conformal coating. Therefore, this is a very attractive bonding tool for many MEMS devices. The bonding strength and uniformity were evaluated using diverse tools. Fracture mechanisms and the effects of bonding parameters and an adhesion promoter were also investigated. The bonding with a structured wafer was also successfully demonstrated.

Morphology and Bond Strength of Copper Wafer Bonding

Abstract: The morphology and bond strength of copper-bonded wafer pairs prepared under different bonding/annealing temperatures and durations are presented. The interfacial morphology was examined by transmission electron microscopy while the bond strength was examined from a diesaw test. Physical mechanisms explaining the different roles of postbonding anneals at temperatures above and below 300°C are discussed. A map summarizing these results provides a useful reference on process conditions suitable for actual microelectronics fabrication and three-dimensional integrated circuits based on Cu wafer bonding. © 2003 The Electrochemical Society. All rights reserved.