Showing papers on "Wafer published in 2005"

Formation of deep via airgaps for three dimensional wafer to wafer interconnect

Abstract: A method for forming deep via airgaps in a semiconductor substrate is disclosed comprising the steps of patterning a hole in the substrate, partly fill said hole with a sacrificial material (e.g. poly-Si), forming spacers on the sidewalls of the unfilled part of the hole (e.g. TEOS) to narrow the opening, removing through said narrowed opening the remaining part of the sacrificial material (e.g. by isotropic etching) and finally sealing the opening of the airgap by depositing a conformal layer (TEOS) above the spacers. The method of forming a deep via airgap is used to create wafer to wafer vertical stacking. After completion of conventional FEOL and BEOL processing the backside of the wafer will be thinned such that the deep via airgap is opened and conductive material can be deposited within said (airgap) via opening and a through wafer or deep via filled with conductive material is created.

Controlled growth of well-aligned ZnO nanorod array using a novel solution method.

Abstract: A simple method of synthesizing nanomaterials and the ability to control the size and position of them are crucial for fabricating nanodevices. In this work, we developed a novel ammonia aqueous solution method for growing well-aligned ZnO nanorod arrays on a silicon substrate. For ZnO nanorod growth, a thin zinc metal seed layer was deposited on a silicon substrate by thermal evaporation. Uniform ZnO nanorods were grown on the zinc-coated silicon substrate in aqueous solution containing zinc nitrate and ammonia water. The growth temperature was as low as 60−90 °C and a 4-in. wafer size scale up was possible. The morphology of a zinc metal seed layer, pH, growth temperature, and concentration of zinc salt in aqueous solution were important parameters to determine growth characteristics such as average diameters and lengths of ZnO nanorods. We could demonstrate the discrete controlled growth of ZnO nanorods using sequential, tailored growth steps. By combining our novel solution method and general photolit...

Methods for depositing, releasing and packaging micro-electromechanical devices on wafer substrates

Abstract: A method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS device from contamination, physical contact, or other deleterious external events. Without additional changes to the MEMS structure between release and wafer bonding and singulation, except for an optional stiction treatment, the MEMS device is best protected and overall process flow is improved. The method is applicable to the production of any MEMS device and is particularly beneficial in the making of fragile micromirrors.

High performance 5nm radius Twin Silicon Nanowire MOSFET (TSNWFET) : fabrication on bulk si wafer, characteristics, and reliability

Abstract: For the first time, we have successfully fabricated gate-all-around twin silicon nanowire transistor (TSNWFET) on bulk Si wafer using self-aligned damascene-gate process With 10nm diameter nanowire, saturation currents through twin nanowires of 264 mA/mum, 111 mA/mum for n-channel TSNWFET and p-channel TSNWFET are obtained, respectively No roll-off of threshold voltages, ~70 mV/dec of substhreshold swing (SS), and ~20 mV/V of drain induced barrier lowering(DIBL) down to 30 nm gate length are observed for both n-ch and p-ch TSNWFETs

Hybrid silicon evanescent laser fabricated with a silicon waveguide and III-V offset quantum wells.

Abstract: A novel laser that utilizes a silicon waveguide bonded to AlGaInAs quantum wells is demonstrated. This wafer scale fabrication approach allows the optical waveguide to be defined by CMOS-compatible silicon processing while optical gain is provided by III-V materials. The AlGaInAs quantum well structure is bonded to the silicon wafer using low temperature oxygen plasma-assisted wafer bonding. The optically pumped 1538 nm laser has a pulsed threshold of 30 mW and an output power of 1.4 mW.

Growth of 2 inch ZnO bulk single crystal by the hydrothermal method

Abstract: Zinc oxide (ZnO) single crystals were grown by the hydrothermal method using a platinum inner container. The 2 inch ZnO wafers obtained from these bulk crystals possess an extremely high crystallinity and purity. The electrical resistivity is highly uniform over the entire wafer area. After annealing, the step-and-terrace structure was observed on the surface of the wafer. The etch pit density was decreased to less than 80 cm−2. These results suggest that these 2 inch ZnO wafers are suitable for wide band gap device applications.

Bendable single crystal silicon thin film transistors formed by printing on plastic substrates

Abstract: Bendable, high performance single crystal silicon transistors have been formed on plastic substrates using an efficient dry transfer printing technique. In these devices, free standing single silicon objects, which we refer to as microstructured silicon (μs‐Si), are picked up, using a conformable rubber stamp, from the top surface of a wafer from which they are generated. The μs‐Si is then transferred, to a specific location and with a controlled orientation, onto a thin plastic sheet. The efficiency of this method is demonstrated by the fabrication of an array of thin film transistors that exhibit excellent electrical properties: average device effective mobilities, evaluated in the linear regime, of ∼240cm2∕Vs, and threshold voltages near 0V. Frontward and backward bending tests demonstrate the mechanical robustness and flexibility of the devices.

Stamp-and-stick room-temperature bonding technique for microdevices

Abstract: Multilayer MEMS and microfluidic designs using diverse materials demand separate fabrication of device components followed by assembly to make the final device. Structural and moving components, labile bio-molecules, fluids and temperature-sensitive materials place special restrictions on the bonding processes that can be used for assembly of MEMS devices. We describe a room temperature "stamp and stick (SAS)" transfer bonding technique for silicon, glass and nitride surfaces using a UV curable adhesive. Alternatively, poly(dimethylsiloxane) (PDMS) can also be used as the adhesive; this is particularly useful for bonding PDMS devices. A thin layer of adhesive is first spun on a flat wafer. This adhesive layer is then selectively transferred to the device chip from the wafer using a stamping process. The device chip can then be aligned and bonded to other chips/wafers. This bonding process is conformal and works even on surfaces with uneven topography. This aspect is especially relevant to microfluidics, where good sealing can be difficult to obtain with channels on uneven surfaces. Burst pressure tests suggest that wafer bonds using the UV curable adhesive could withstand pressures of 700 kPa (7 atmospheres); those with PDMS could withstand 200 to 700 kPa (2-7 atmospheres) depending on the geometry and configuration of the device.

Design and fabrication of a hybrid silicon three-axial force sensor for biomechanical applications

Abstract: This paper presents the design and development of a silicon-based three-axial force sensor to be used in a flexible smart interface for biomechanical measurements. Normal and shear forces are detected by combining responses from four piezoresistors obtained by ion implantation in a high aspect-ratio cross-shape flexible element equipped with a 525 m high silicon mesa. The mesa is obtained by a subtractive dry etching process of the whole handle layer of an SOI wafer. Piezoresistor size ranges between 6 and 10m in width, and between 30 and 50m in length. The sensor configuration follows a hybrid integration approach for interconnection and for future electronic circuitry system integration. The sensor ability to measure both normal and shear forces with high linearity ( ∼99%) and low hysteresis is demonstrated by means of tests performed by applying forces from 0 to 2 N. In this paper the packaging design is also presented and materials for flexible sensor array preliminary assembly are described. © 2005 Elsevier B.V. All rights reserved.

3D integrated circuits using thick metal for backside connections and offset bumps

Abstract: Backside connections for 3D integrated circuits and methods to fabricate thereof are described. A stack of a first wafer over a second wafer that has a substrate of the first wafer on top of the stack, is formed. The substrate of the first wafer is thinned. A first dielectric layer is deposited on the thinned substrate. First vias extending through the substrate to the first wafer are formed in the first dielectric layer. A conductive layer is deposited in the first vias and on the first dielectric layer to form thick conductive lines. Second dielectric layer is formed on the conductive layer. Second vias extending to the conductive lines are formed in the second dielectric layer. Conductive bumps extending into the second vias and offsetting the first vias are formed on the second dielectric layer.

Accessible chip stack and process of manufacturing thereof

Abstract: A process of manufacturing a three-dimensional integrated circuit chip or wafer assembly and, more particularly, a processing of chips while arranged on a wafer prior to orienting the chips into stacks. Also disclosed is the manufacture of the three-dimensional integrated circuit wherein the chip density can be very high and processed while the wafers are still intact and generally of planar constructions.

Method for manufacturing wafer level chip stack package

Abstract: Provided is a method for manufacturing WLCSP devices that includes preparing at least two wafers, each wafer having a plurality of corresponding semiconductor chips, each semiconductor chip having through electrodes formed in the peripheral surface region, forming or applying a solid adhesive region to a central surface region, stacking a plurality of wafers and attaching corresponding chips provided on adjacent wafers with the solid adhesive region and connecting corresponding through electrodes of adjacent semiconductor chips, dividing the stacked wafers into individual chip stack packages, and injecting a liquid adhesive into a space remaining between adjacent semiconductor chips incorporated in the resulting chip stack package. By reducing the likelihood of void regions between adjacent semiconductor chips, it is expected that a method according to the exemplary embodiments of the present invention exhibit improved mechanical stability and reliability.

Method of dividing wafer

Abstract: In order to efficiently divide the wafer into individual devices in dicing the wafer without deteriorating the quality of the devices, the front surface of the wafer is coated with a resist film except the regions corresponding to the streets, grooves of a depth corresponding to the finished thickness of the devices are formed by plasma etching in the regions corresponding to the streets, and the back surface of the wafer is ground so that the grooves are exposed from the side of the back surface and that the wafer is divided into individual devices.

Method to perform selective atomic layer deposition of zinc oxide

Abstract: A method for selective ALD of ZnO on a wafer preparing a silicon wafer; patterning the silicon wafer with a blocking agent in selected regions where deposition of ZnO is to be inhibited, wherein the blocking agent is taken from a group of blocking agents includes isopropyl alcohol, acetone and deionized water; depositing a layer of ZnO on the wafer by ALD using diethyl zinc and H 2 O at a temperature of between about 140° C. to 170° C.; and removing the blocking agent from the wafer.

New substrate passivation method dedicated to HR SOI wafer fabrication with increased substrate resistivity

Abstract: We propose in this letter a new passivation method to get rid of parasitic surface conduction in oxidized high resistivity (HR) silicon and HR silicon-on-insulator (SOI) wafers. The method consists in passivating the HR substrate with a rapid thermal anneal (RTA)-crystallized layer of silicon. The electrical efficiency of this new passivation technique is analyzed and shown to be superior over previously published methods. The surface roughness as well as the stability over temperature of this layer are also investigated. It is shown that this new passivation method is the only one simultaneously combining a low surface roughness and a high stability over long thermal anneals. In the context of SOI technology, it therefore appears as the most suitable technique for the substrate passivation of HR SOI wafers, for which a bonding between an oxidized silicon wafer and a passivated HR substrate is required.

Method of forming a thin wafer stack for a wafer level package

Abstract: A method of forming a stack of thin wafers provides a wafer level stack to greatly reduce process time compared to a method where individually separated chips are stacked after a wafer is sawed. A rigid planar wafer support member stabilizes and planarizes each wafer while it is thin or its thickness is reduced and during subsequent wafer processing. Thinned wafers are stacked and the external support members are removed by applying heat or ultraviolet (UV) light to an expandable adhesive layer between the support members and the thin wafers. The stacked wafers then can be further processed and packaged without thin-wafer warping, cracking or breaking. A wafer level package made in accordance with the invented method also is disclosed.

Wafer holder for wafer prober and wafer prober equipped with same

Abstract: The invention provides a wafer-prober wafer holder that allows positional precision and temperature uniformity to be increased, and also allows the chip to be heated and cooled rapidly, and a wafer prober device provided with the same. The wafer-prober wafer holder of the invention is constituted by a chuck top having a chuck top conducting layer on its surface, and a support member for supporting the chuck top, and has a cavity in a portion between the chuck top and the support member. The chuck top preferably is provided with a heating member.

Manufacturing method of semiconductor device

Abstract: PROBLEM TO BE SOLVED: To realize the manufacturing method of a semiconductor device, sharply reduced in the occurrence of local cracks and fractures of a thinly processed semiconductor wafer, and further sharply reduced in chippings and cracks the cut surface of a semiconductor chip diced. SOLUTION: A rear surface 4 of the semiconductor wafer 1 is polished, by sticking on a semiconductor element forming surface 2 a first protective tape 3a for protecting various semiconductor elements provided on the semiconductor element formation surface 2. Full cut dicing is implemented, where a second protective tape 3b on the rear surface 4 of the semiconductor wafer 1 is cut, up to a part thereof after transfer, to separate the semiconductor wafer 1 processed to be thin to a plurality of the semiconductor chips 30. After transfer, chemical dry etching (CDE) is applied, to make the surface roughness (Ra) of the rear surface 4 of the semiconductor chip 30≥0.05μm, for example, and hereby to remove minute chippings, microcracks, and crushed layers or the like on the cut surface of the semiconductor chip 30. COPYRIGHT: (C)2006,JPO&NCIPI

Microfabrication of 3D silicon MEMS structures using gray-scale lithography and deep reactive ion etching

Abstract: Micromachining arbitrary 3D silicon structures for micro-electromechanical systems can be accomplished using gray-scale lithography along with dry anisotropic etching. In this study, we have investigated the use of deep reactive ion etching (DRIE) and the tailoring of etch selectivity for precise fabrication. Silicon loading, the introduction of an O 2 step, wafer electrode power, and wafer temperature are evaluated and determined to be effective for coarsely controlling etch selectivity in DRIE. The non-uniformity and surface roughness characteristics are evaluated and found to be scaled by the etch selectivity when the 3D profile is transferred into the silicon. A micro-compressor is demonstrated using gray-scale lithography and DRIE showing that etch selectivity can be successfully tailored for a specific application. © 2004 Elsevier B.V. All rights reserved.

Multi-single wafer processing apparatus

Abstract: A wafer processing apparatus includes one or more processing modules, each having multiple, distinct, single-wafer processing reactors configured for semi-independent ALD and/or CVD film deposition therein; a robotic central wafer handler configured to provide wafers to and accept wafers from each of said wafer processing modules; and a single-wafer loading and unloading mechanism that includes a loading and unloading port and a mini-environment coupling the loading and unloading port to the robotic central wafer handler. The wafer processing reactors may be arranged (I) along axes of a Cartesian coordinate system, or (I) in quadrants defined by said axes, one axis being parallel to a wafer input plane of the at least one of the process modules to which the single-wafer processing reactors belong. Each processing module can include up to four single-wafer processing reactors, each with an independent gas distribution module.

Substrate processing apparatus and substrate processing method

Abstract: An aging unit (DAC) for processing a wafer W having a coated film formed thereon includes a disposing plate, a temperature control circulating device for controlling the temperature of the disposing plate, a chamber, a gas supply mechanism for supplying an ammonia gas containing a water vapor into the chamber, an input section for inputting the processing time of the wafer W, and a control device for controlling the temperature of the disposing plate, the supply rate of the ammonia gas, and the amount of the water vapor contained in the ammonia gas so as to permit the processing of the wafer W to be finished in the processing time inputted into the input section

Manufacturing method for semiconductor devices, and formation apparatus for semiconductor wafer dicing masks

Abstract: On a mask placement-side surface of a semiconductor wafer in which a plurality of semiconductor devices are formed, a mask is placed, while dicing lines for dicing the semiconductor wafer into the respective separate semiconductor devices are defined and a surface of a flawed semiconductor device among the respective semiconductor devices is partially exposed, and then plasma etching is applied to the mask placement-side surface of the semiconductor wafer so as to dice the semiconductor wafer into the respective semiconductor devices along the defined dicing lines, and an exposed portion of the flawed semiconductor device is removed so as to form a removed portion as a flawed semiconductor device distinguishing mark.

Multi-station deposition apparatus and method

Abstract: A multi-station deposition apparatus capable of simultaneous processing multiple substrates using a plurality of stations, where a gas curtain separates the stations. The apparatus further comprises a multi-station platen that supports a plurality of wafers and rotates the wafers into specific deposition positions at which deposition gases are supplied to the wafers. The deposition gases may be supplied to the wafer through single zone or multi-zone gas dispensing nozzles.

Low temperature absorption layer deposition and high speed optical annealing system

Abstract: An integrated system for processing a semiconductor wafer includes a toroidal source plasma reactor for depositing a heat absorbing layer, the reactor including a wafer support, a reactor chamber, an external reentrant toroidal conduit coupled to said chamber on generally opposing sides thereof, an RF source power applicator for coupling power to a section of said external reentrant conduit and a process gas source containing a heat absorbing material precursor gas. The integrated system further includes an optical annealing chamber.

Glass frit bonding: an universal technology for wafer level encapsulation and packaging

Abstract: This paper reports on glass frit wafer bonding, which is a universally usable technology for wafer level encapsulation and packaging. After explaining the principle and the process flow of glass frit bonding, experimental results are shown. Glass frit bonding technology enables bonding of surface materials commonly used in MEMS technology. It allows hermetic sealing and a high process yield. Metal lead throughs at the bond interface are possible, because of the planarizing glass interlayer. Examples of surface micromachined sensors demonstrate the potential of glass–frit bonding.

Ordered silicon nanocavity arrays in surface-assisted desorption/ionization mass spectrometry.

Abstract: We report here a simple method to generate ordered nanocavity arrays on a Si wafer and use it in surface-assisted laser desorption/ionization mass spectrometry (SALDI-MS). A close-packed SiO2 nanosphere array was first deposited on a low-resistivity Si wafer using a convective self-assembly method. The nanoparticle array was then used as a mask in a reactive ion etching (RIE) process to selectively remove portions of the Si surface. Subsequent sonication removed those physically adsorbed SiO2 nanoparticles and exposed an ordered nanocavity array underneath. The importance of this approach is its capability of systematically varying surface geometries to achieve desired features, which makes detailed studies of the impacts of surface features on the desorption/ionization mechanism feasible. We demonstrated that the in-plane width and out-of-plane depth of the cavities were adjustable by varying etching times, and the intercavity spacing was controllable by varying the number of particle layers deposited. M...

Device and method for fabricating double-sided soi wafer scale package with through via connections

Abstract: A semiconductor package includes an SOI wafer having a first side including an integrated circuit system, and a second side, opposite the first side, forming at least one cavity. At least one chip or component is placed in the cavity. An optical through via is formed through a buried oxide which optically connects the chip(s) to the integrated circuit system.