Showing papers on "Wafer published in 2008"

Wafer-scale assembly of highly ordered semiconductor nanowire arrays by contact printing.

Abstract: Controlled and uniform assembly of “bottom-up” nanowire (NW) materials with high scalability presents one of the significant bottleneck challenges facing the integration of nanowires for electronic...

Preparation of Large-Area Uniform Silicon Nanowires Arrays through Metal-Assisted Chemical Etching

Abstract: A facile fabricating method has been established for large-area uniform silicon nanowires arrays All silicon nanowires obtained were single crystals and epitaxial on the substrate Six kinds of silicon wafers with different types, surface orientations, and doping levels were utilized as starting materials With the catalysis of silver nanoparticles, room-temperature mild chemical etching was conducted in aqueous solution of hydrofluoric acid (HF) and hydrogen peroxide (H2O2) The corresponding silicon nanowires arrays with different morphologies were obtained The silicon nanowires possess the same type and same doping level of the starting wafer All nanowires on the substrate have the same orientation For instance, both (100)- and (111)-oriented p-type wafers produced silicon nanowires in the (100) direction For every kind of silicon wafer, the effect of etching conditions, such as components of etchant, temperature, and time, were systemically investigated This is an appropriate method to produce a

Silicon nanowires for rechargeable lithium-ion battery anodes

Abstract: Large-area, wafer-scale silicon nanowire arrays prepared by metal-induced chemical etching are shown as promising scalable anode materials for rechargeable lithium battery. In addition to being low cost, large area, and easy to prepare, the electroless-etched silicon nanowires (SiNWs) have good conductivity and nanometer-scale rough surfaces; both features facilitate charge transport and insertion/extraction of Li ions. The electroless-etched SiNWs anode showed larger charge capacity and longer cycling stability than the conventional planar-polished Si wafer.

Motility of metal nanoparticles in silicon and induced anisotropic silicon etching

Abstract: The autonomous motion behavior of metal particles in Si, and the consequential anisotropic etching of silicon and production of Si nanostructures, in particular, Si nanowire arrays in oxidizing hydrofluoric acid solution, has been systematically investigated. It is found that the autonomous motion of metal particles (Ag and Au) in Si is highly uniform, yet directional and preferential along the [100] crystallographic orientation of Si, rather than always being normal to the silicon surface. An electrokinetic model has been formulated, which, for the first time, satisfactorily explains the microscopic dynamic origin of motility of metal particles in Si. According to this model, the power generated in the bipolar electrochemical reaction at a metal particle's surface can be directly converted into mechanical work to propel the tunneling motion of metal particles in Si. The mechanism of pore and wire formation and their dependence on the crystal orientation are discussed. These models not only provide fundamental interpretation of metal-induced formation of pits, porous silicon, and silicon nanowires and nanopores, they also reveal that metal particles in the metal/Si system could work as a self-propelled nanomotor. Significantly, it provides a facile approach to produce various Si nanostructures, especially ordered Si nanowire arrays from Si wafers of desired properties.

Wafer-scale silicon nanopillars and nanocones by Langmuir-Blodgett assembly and etching

Abstract: We have developed a method combining Langmuir–Blodgett assembly and reactive ion etching to fabricate nanopillars with uniform coverage over an entire 4 inch wafer. We demonstrated precise control over the diameter and separation between the nanopillars ranging from 60 to 600 nm. We can also change the shape of the pillars from having vertical to tapered sidewalls with sharp tips exhibiting a radius of curvature of 5 nm. This method opens up many possible opportunities in nanoimprinting, solar cells, batteries, and scanning probes.

Wafer level packaging of MEMS

Abstract: Wafer level packaging plays many important roles for MEMS (micro electro mechanical systems), including cost, yield and reliability. MEMS structures on silicon chips are encapsulated between bonded wafers or by surface micromachining, and electrical interconnections are made from the cavity. Bonding at the interface, such as glass–Si anodic bonding and metal-to-metal bonding, requires electrical interconnection through the lid vias in many cases. On the other hand, lateral electrical interconnections on the surface of the chip are used for bonding with intermediate melting materials, such as low melting point glass and solder. The cavity formed by surface micromachining is made using sacrificial etching, and the openings needed for the sacrificial etching are plugged using deposition sealing methods. Vacuum packaging methods and the structures for electrical feedthrough for the interconnection are discussed in this review.

Embedded wafer level ball grid array (eWLB)

Abstract: The main challenges of today's device packaging are miniaturization, continuously increasing operating frequencies/high data rates, high number of I/Os, reliability, and thermal requirements. One of the major package trends driven by mobile-phone applications is the Wafer Level Ball Grid Array (WLB). Drivers for the implementation of WLB technology are cost reduction, smaller form factor and better electrical performance with respect to high frequency applications. Thin-film WLB technology consists in realizing additional redistribution layers above the passivation of a semiconductor chip using standard thin-film techniques to rearrange peripheral pads on the wafer in an array pattern. A hard limit will be reached with this technology, when the number of I/Os reaches a larger number dian can be fitted on the silicon chip at a given pitch. We introduce Infineon's embedded Wafer Level Ball Grid Array technology, which allows fitting interconnects onto a so-called fan-out area extending the chip area. The core process of this emerging technology is the encapsulation of silicon dice by compression molding. The eWLB technology is a forward-looking development of the WLB technology, upholding the known benefits such as small package dimensions, excellent electrical and thermal performance, and maximum connection density. However, this technology significantly increases the functionality and application spread. Due to eWLB. complex semiconductor chips such as modem and processor chips for applications in mobile communications require a high number of solder connections with standardized contact spacing to be produced with a minimal footprint. At the same time, the packages can be provided with as many solder contacts as needed. The possibility of additional wiring area around the chip proper means that the wafer-level packaging technology also lends itself to new. space-sensitive applications. We demonstrate the capabilities of Infineon's molded embedded Wafer Level Package Technology and show how we extended it towards a Platform Technology. The qualified Platform we introduce here covers currently a range of package sizes up to 8×8mm2 at a ball pitch of 0.5mm. The Qualification Criteria we have applied follow the tests described in JEDEC Standard Number 26-A.

Wafer-scale patterning of sub-40 nm diameter and high aspect ratio (>50:1) silicon pillar arrays by nanoimprint and etching

Abstract: We demonstrate wide-area fabrication of sub-40 nm diameter, 1.5 µm tall, high aspect ratio silicon pillar arrays with straight sidewalls by combining nanoimprint lithography (NIL) and deep reactive ion etching (DRIE). Imprint molds were used to pre-pattern nanopillar positions precisely on a 200 nm square lattice with long range order. The conventional DRIE etching process was modified and optimized with reduced cycle times and gas flows to achieve vertical sidewalls; with such techniques the pillar sidewall roughness can be reduced below 8 nm (peak-to-peak). In some cases, sub-50 nm diameter pillars, 3 µm tall, were fabricated to achieve aspect ratios greater than 60:1.

Method of forming silicon-containing films

Abstract: A method of forming a silicon-containing film comprising providing a substrate in a reaction chamber, injecting into the reaction chamber at least one silicon-containing compound; injecting into the reaction chamber at least one co-reactant in the gaseous form; and reacting the substrate, silicon-containing compound, and co-reactant in the gaseous form at a temperature equal to or less than 550°C to obtain a silicon-containing film deposited onto the substrate. A method of preparing a silicon nitride film comprising introducing a silicon wafer to a reaction chamber; introducing a silicon-containing compound to the reaction chamber; purging the reaction chamber with an inert gas; and introducing a nitrogen-containing co-reactant in gaseous form to the reaction chamber under conditions suitable for the formation of a monomolecular layer of a silicon nitride film on the silicon wafer.

Solar cell and method of manufacture

Abstract: A solar cell that is readily manufactured using processing techniques which are less expensive than microelectronic circuit processing. In preferred embodiments, printing techniques are utilized in selectively forming masks for use in etching of silicon oxide and diffusing dopants and in forming metal contacts to diffused regions. In a preferred embodiment, p-doped regions and n-doped regions are alternately formed in a surface of the wafer through use of masking and etching techniques. Metal contacts are made to the p-regions and n-regions by first forming a seed layer stack that comprises a first layer such as aluminum that contacts silicon and functions as an infrared reflector, second layer such titanium tungsten that acts as diffusion barrier, and a third layer functions as a plating base. A thick conductive layer such as copper is then plated over the seed layer, and the seed layer between plated lines is removed. A front surface of the wafer is preferably textured by etching or mechanical abrasion with an IR reflection layer provided over the textured surface. A field layer can be provided in the textured surface with the combined effect being a very low surface recombination velocity.

Design and fabrication of MEMS thermoelectric generators with high temperature efficiency

Abstract: For MEMS devices with power consumption in the range of micro-watts, thermal energy harvesting becomes a viable candidate for power supply. This paper describes a multipurpose platform to fabricate thermoelectric generators in a combined surface and bulk micromachining process. The thermocouples are deposited by thin-film processes with high integration density on the wafer surface. To provide a large thermal contact area, the heat flow path is perpendicular to the chip surface (cross-plane) and guided by thermal connectors. One thermocouple junction is thermally connected via electroplated metal stripes to the heat source and thermally insulated to the heat sink by a cavity in the wafer substrate. Simulations show that approximately 95% of the entire temperature difference over the device is located between the two thermocouple junctions. Power factors of 3.63 × 10 −3 μW mm −2 K −2 and 8.14 × 10 −3 μW mm −2 K −2 can be achieved with thermopiles made of Al and n-poly-Si or p-Bi 0.5 Sb 1.5 Te 3 and n-Bi 0.87 Sb 0.13 , respectively. Measurements of fabricated devices show a linear output voltage of 76.08 μV K −1 per thermocouple and prove the feasibility of the concept.

Surface‐Dominated Transport Properties of Silicon Nanowires

Abstract: Surface effects are widely recognized to significantly influence the properties of nanostructures, although the detailed mechanisms are rarely studied and unclear. Herein we report for the first time a quantitative evaluation of the surface-related contributions to transport properties in nanostructures by using Si nanowires (NWs) as a paradigm. Critical to this study is the capability of synthesizing SiNWs with predetermined conduction type and carrier concentration from Si wafer of known properties using the recently developed metal-catalyzed chemical etching method. Strikingly, the conductance of p-type SiNWs is is substantively larger in air than that of the original wafer, is sensitive to humidity and volatile gases, and thinner wires show higher conductivity. Further, SiNW-based field-effect transistors (FETs) show NWs to have a hole concentration two orders of magnitude higher than the original wafer. In vacuum, the conductivity of SiNWs dramatically decreases, whereas hole mobility increases. The device performances are further improved by embedding SiNW FETs in 250 nm SiO 2, which insulates the devices from atmosphere and passivates the surface defects of NWs. Owing to the strong surface effects, n-type SiNWs even change to exhibit p-type characteristics. The totality of the results provides definitive confirmation that the electrical characteristics of SiNWs are dominated by surface states. A model based on surface band bending and carrier scattering caused by surface states is proposed to interpret experimental results. The phenomenon of surface-dependent transport properties should be generic to all nanoscale structures, and is significant for nanodevice design for sensor and electronic applications.

Wafer processing apparatus with wafer alignment device

Abstract: A semiconductor-processing apparatus includes: a wafer handling chamber; a wafer processing chamber; a wafer handling device; a first photosensor disposed in the wafer handling chamber in front of the wafer processing chamber at a position where the wafer partially blocks light received by the first photosensor at a ready-to-load position and substantially entirely blocks light received by the first photosensor when the wafer moves from the ready-to-load position toward the wafer processing chamber in the x-axis direction; and a second photosensor disposed in the wafer handling chamber in front of the wafer processing chamber at a position where the wafer does not block light received by the second photosensor at the ready-to-load position and partially blocks light received by the second photosensor when the wafer moves from the ready-to-load position toward the wafer processing chamber in the x-axis direction.

Temperature measurement and control of wafer support in thermal processing chamber

Abstract: The present invention provides apparatus and methods for achieving uniform heating to a substrate during a rapid thermal process. More particularly, the present invention provides apparatus and methods for controlling the temperature of an edge ring supporting a substrate during a rapid thermal process to improve temperature uniformity across the substrate.

Direct synthesis and properties of K2SiF6:Mn4+ phosphor by wet chemical etching of Si wafer

Abstract: A new method of synthesizing Mn-activated phosphor is presented The method uses only chemical etching of Si wafer in HF/H2O solution with the addition of an oxidizing agent KMnO4 The luminescence centers of red emission are ascribed to Mn4+ ions in the octahedral sites of potassium hexafluorosilicate (K2SiF6) The luminescence intensity becomes much stronger at higher temperatures, without largely changing its spectral feature

Apparatus for etching semiconductor wafers

Abstract: A wafer pedestal of a semiconductor apparatus is provided. The wafer pedestal is capable of supporting a substrate. The wafer pedestal includes a pedestal having at least one purge opening configured to flow a purge gas and at least one chucking opening configured to chuck the substrate over the pedestal. The pedestal includes a sealing band disposed between the at least one purge opening and the at least one chucking opening. The sealing band is configured to support the substrate.

3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections

Abstract: Three-dimensional (3D) integration using through-silicon vias (TSVs) and low-volume lead-free solder interconnects allows the formation of high signal bandwidth, fine pitch, and short-distance interconnections in stacked dies. There are several approaches for 3D chip stacking including chip to chip, chip to wafer, and wafer to wafer. Chip-to-chip integration and chip-to-wafer integration offer the ability to stack known good dies, which can lead to higher yields without integrated redundancy. In the future, with structure and process optimization, wafer-to-wafer integration may provide an ultimate solution for the highest manufacturing throughput assuming a high yield and minimal loss of good dies and wafers. In the near term, chip-to-chip and chip-to-wafer integration may offer high yield, high flexibility, and high performance with added time-to-market advantages. In this work, results are reported for 3D integration after using a chip-to-wafer assembly process using 3D chip-stacking technology and fine-pitch interconnects with lead-free solder. Stacks of up to six dies were assembled and characterized using lead-free solder interconnections that were less than 6 µm in height. The average resistance of the TSV including the lead-free solder interconnect was as low as 21 mΩ.

Wafer transfer blade

Abstract: Projections 22 of the blade 16 provided on a blade surface in a wafer-loading region 18 b of a body 18 support a wafer W loaded on the blade surface 18 a. Since the projections 22 have microgrooves formed by surface roughening the wafer W is retained on the projections 22 with a suppressed displacement. The blade 16 has a simple structure that retains the wafer W without vacuum suction and has no receiving hole to retain the wafer W in the body 18 of the blade 16. This can effectively prevent formation of defects on the wafer W.

Tungsten-Based SOI Microhotplates for Smart Gas Sensors

Abstract: This paper is concerned with the design, fabrication, and characterization of novel high-temperature silicon on insulator (SOI) microhotplates employing tungsten resistive heaters. Tungsten has a high operating temperature and good mechanical strength and is used as an interconnect in high temperature SOI-CMOS processes. These devices have been fabricated using a commercial SOI-CMOS process followed by a deep reactive ion etching (DRIE) back-etch step, offering low cost and circuit integration. In this paper, we report on the design of microhotplates with different diameters (560 and 300 mum) together with 3-D electrothermal simulation in ANSYS, electrothermal characterization, and analytical analysis. Results show that these devices can operate at high temperatures (600degC ) well beyond the typical junction temperatures of high temperature SOI ICs (225degC), have ultralow dc power consumption (12 mW at 600degC), fast transient time (as low as 2-ms rise time to 600degC), good thermal stability, and, more importantly, a high reproducibility both within a wafer and from wafer to wafer. We also report initial tests on the long-term stability of the tungsten heaters. We believe that this type of SOI microhotplate could be exploited commercially in fully integrated microcalorimetric or resistive gas sensors.

Grinding of silicon wafers: A review from historical perspectives

Abstract: The majority of semiconductor devices are built on silicon wafers. Manufacturing of high-quality silicon wafers involves several machining processes including grinding. This review paper discusses historical perspectives on grinding of silicon wafers, impacts of wafer size progression on applications of grinding in silicon wafer manufacturing, and interrelationships between grinding and two other silicon machining processes (slicing and polishing). It is intended to help readers to gain a more comprehensive view on grinding of silicon wafers, and to be instrumental for research and development in grinding of wafers made from other materials (such as gallium arsenide, germanium, lithium niobate, sapphire, and silicon carbide).

Manufacturing method of a silicon carbide semiconductor device

Abstract: A manufacturing method for a silicon carbide semiconductor device is disclosed. It includes an etching method in which an Al film and Ni film are laid on an SiC wafer in this order and wet-etched, whereby a two-layer etching mask is formed in which Ni film portions overhang Al film portions. Mesa grooves are formed by dry etching by using this etching mask.

Plasma process employing multiple zone gas distribution for improved uniformity of critical dimension bias

Abstract: A passivation species precursor gas is furnished to an inner zone at a first flow rate, while flowing an etchant species precursor gas an annular intermediate zone at a second flow rate. Radial distribution of etch rate is controlled by the ratio of the first and second flow rates. The radial distribution of etch critical dimension bias on the wafer is controlled by flow rate of passivation gas to the wafer edge.

Imaging module with symmetrical lens system and method of manufacture

Abstract: An imaging module and method of fabrication. The method comprises forming a first lens wafer with a plurality of outer negative lenses and forming a second lens wafer with a plurality of inner negative lenses The method further comprises bonding the first lens wafer and second lens wafer to create a bonded stack; forming a plurality of inner positive lenses on the second lens wafer and bonding a spacer wafer to the second lens wafer; and forming a plurality of outer positive lenses on the first lens wafer.

Trimming of silicon ring resonator by electron beam induced compaction and strain.

Abstract: Silicon is becoming the preferable platform for future integrated components, mostly due to the mature and reliable fabrication capabilities of electronics industry. Nevertheless, even the most advanced fabrication technologies suffer from non-uniformity on wafer scale and on chip scale, causing variations in the critical dimensions of fabricated components. This is an important issue since photonic circuits, and especially cavities such as ring resonators, are extremely sensitive to these variations. In this paper we present a way to circumvent these problems by trimming using electron beam induced compaction of oxide in silicon on insulator. Volume compaction of the oxide cladding causes both changes in the refractive index and creates strain in the silicon lattice. We demonstrate a resonance wavelength red shift 4.91 nm in a silicon ring resonator.

Reliable metal bumps on top of I/O pads after removal of test probe marks

Abstract: In accordance with the objectives of the invention a new method is provided for the creation of metal bumps over surfaces of I/O pads. Contact pads are provided over the surface of a layer of dielectric. The aluminum of the I/O pads, which have been used as I/O pads during wafer level semiconductor device testing, is completely or partially removed over a surface area that is smaller than the surface area of the contact pad using methods of metal dry etching or wet etching. The contact pad can be accessed either by interconnect metal created in a plane of the contact pad or by via that are provided through the layer of dielectric over which the contact pad has been deposited. The process can be further extended by the deposition, patterning and etching of a layer of polyimide over the layer of passivation that serves to protect the contact pad.

Manufacturing method of fin-type field effect transistor

Abstract: A method for manufacturing a fin-type field effect transistor simply and securely by using a SOI (Silicon On Insulator) wafer, capable of suppressing an undercut formation, is disclosed. The method includes forming a fin-shaped protrusion by selectively dry-etching a single crystalline silicon layer until an underlying buried oxide layer is exposed; forming a sacrificial oxide film by oxidizing a surface of the protrusion including a damage inflicted thereon; and forming a fin having a clean surface by removing the sacrificial oxide film by etching, wherein an etching rate r 1 of the sacrificial oxide film is higher than an etching rate r 2 of the buried oxide layer during the etching.

Surface passivation and heterojunction cells on Si (100) and (111) wafers using dc and rf plasma deposited Si:H thin films

Abstract: The structure of hydrogenated silicon (Si:H) films deposited by rf and dc plasma process on Si (100) and (111) wafers is correlated with the surface passivation quality and heterojunction cell performance. Microstructural defects associated with SiH2 bonding and apparent ion bombardment in dc plasmas have little or no adverse effect on passivation or cell properties, while presence of crystallinity in Si:H i layer severely deteriorates surface passivation and cell open circuit voltage (Voc). Excellent surface passivation (lifetime of >1ms) and high efficiency cells (>18%) with Voc of 694mV are demonstrated on n-type textured Czochralski wafer using dc plasma process.

Susceptor and method for manufacturing silicon epitaxial wafer

Abstract: Provided is a susceptor (13) for manufacturing an epitaxial wafer. The susceptor is provided with a mesh-like groove (13b) on a placing surface whereupon a silicon substrate (W) is to be placed. On the placing surface, a silicon carbide film (H) is formed. The film (H) has a surface roughness of 1μm or more in center line average roughness (Ra), and a protrusion (13p) generated at the time of applying the film (H) has a maximum height of 5μm or less. Thus, not only attaching of the silicon substrate with the susceptor but also generation of defects such as warping and slip are eliminated.

Metallic Nanowires by Full Wafer Stencil Lithography

Abstract: Aluminum and gold nanowires were fabricated using 100 mm stencil wafers containing nanoslits fabricated with a focused ion beam. The stencils were aligned and the nanowires deposited on a substrate with predefined electrical pads. The morphology and resistivity of the wires were studied. Nanowires down to 70 nm wide and 5 µm long have been achieved showing a resistivity of 10 µΩcm for Al and 5 µΩcm for Au and maximum current density of ∼10 8 A/cm 2 . This proves the capability of stencil lithography for the fabrication of metallic nanowires on