Showing papers on "Wafer published in 2009"

X-ray diffraction of III-nitrides

Abstract: The III-nitrides include the semiconductors AlN, GaN and InN, which have band gaps spanning the entire UV and visible ranges. Thin films of III-nitrides are used to make UV, violet, blue and green light-emitting diodes and lasers, as well as solar cells, high-electron mobility transistors (HEMTs) and other devices. However, the film growth process gives rise to unusually high strain and high defect densities, which can affect the device performance. X-ray diffraction is a popular, non-destructive technique used to characterize films and device structures, allowing improvements in device efficiencies to be made. It provides information on crystalline lattice parameters (from which strain and composition are determined), misorientation (from which defect types and densities may be deduced), crystallite size and microstrain, wafer bowing, residual stress, alloy ordering, phase separation (if present) along with film thicknesses and superlattice (quantum well) thicknesses, compositions and non-uniformities. These topics are reviewed, along with the basic principles of x-ray diffraction of thin films and areas of special current interest, such as analysis of non-polar, semipolar and cubic III-nitrides. A summary of useful values needed in calculations, including elastic constants and lattice parameters, is also given. Such topics are also likely to be relevant to other highly lattice-mismatched wurtzite-structure materials such as heteroepitaxial ZnO and ZnSe.

Wafer-scale fabrication of separated carbon nanotube thin-film transistors for display applications.

Abstract: Preseparated, semiconductive enriched carbon nanotubes hold great potential for thin-film transistors and display applications due to their high mobility, high percentage of semiconductive nanotubes, and room-temperature processing compatibility. Here in this paper, we report our progress on wafer-scale processing of separated nanotube thin-film transistors (SN-TFTs) for display applications, including key technology components such as wafer-scale assembly of high-density, uniform separated nanotube networks, high-yield fabrication of devices with superior performance, and demonstration of organic light-emitting diode (OLED) switching controlled by a SN-TFT. On the basis of separated nanotubes with 95% semiconductive nanotubes, we have achieved solution-based assembly of separated nanotube thin films on complete 3 in. Si/SiO2 wafers, and further carried out wafer-scale fabrication to produce transistors with high yield (>98%), small sheet resistance (∼25 kΩ/sq), high current density (∼10 μA/μm), and super...

Single crystalline mesoporous silicon nanowires.

Abstract: Herein we demonstrate a novel electroless etching synthesis of monolithic, single-crystalline, mesoporous silicon nanowire arrays with a high surface area and luminescent properties consistent with conventional porous silicon materials. These porous nanowires also retain the crystallographic orientation of the wafer from which they are etched. Electron microscopy and diffraction confirm their single-crystallinity and reveal the silicon surrounding the pores is as thin as several nanometers. Confocal fluorescence microscopy showed that the photoluminescence (PL) of these arrays emanate from the nanowires themselves, and their PL spectrum suggests that these arrays may be useful as photocatalytic substrates or active components of nanoscale optoelectronic devices.

Metal-Catalyst-Free Growth of Single-Walled Carbon Nanotubes

Abstract: We present a metal-catalyst-free CVD process for the high-efficiency growth of single-walled carbon nanotubes (SWNTs) on surface. By applying a 30-nm-thick SiO(2) sputtering deposited Si or Si/SiO(2) wafer as substrate and CH(4) as a carbon source, dense and uniform SWNT networks with high quality can be obtained without the presence of any metal species. Moreover, a simple patterned growth approach, using a scratched Si/SiO(2) wafer as substrate, is also presented for the growth of SWNTs with good position controllability. Our finding of the growth of SWNTs via a metal-catalyst-free process will provide valuable information for understanding the growth mechanism of SWNTs in-depth, which accordingly will facilitate the controllable synthesis and applications of carbon nanotubes.

Atomic layer deposition apparatus

Abstract: A method and apparatus for atomic layer deposition (ALD) is described. The apparatus comprises a deposition chamber and a wafer support. The deposition chamber is divided into two or more deposition regions that are integrally connected one to another. The wafer support is movable between the two or more interconnected deposition regions within the deposition chamber.

Wafer-Scale Growth and Transfer of Aligned Single-Walled Carbon Nanotubes

Abstract: Experimental demonstration of wafer-scale growth of well-aligned, dense, single-walled carbon nanotubes on 4" ST-cut quartz wafers is presented. We developed a new carbon nanotube (CNT) wafer-scale growth process. This process allows quartz wafers to be heated to the CNT growth temperature of 865degC through the alpha-beta phase transformation temperature of quartz (573degC) without wafer fracture. We also demonstrate wafer-scale CNT transfer to transfer these aligned CNTs from quartz wafers to silicon wafers. The CNT transfer process preserves CNT density and alignment. Carbon nanotube FETs fabricated using these transferred CNTs exhibit high yield. Wafer-scale growth and wafer-scale transfer of aligned CNTs enable carbon nanotube very large-scale integration circuits and their large-scale integration with silicon CMOS.

Two- and three-dimensional folding of thin film single-crystalline silicon for photovoltaic power applications

Abstract: Fabrication of 3D electronic structures in the micrometer-to-millimeter range is extremely challenging due to the inherently 2D nature of most conventional wafer-based fabrication methods. Self-assembly, and the related method of self-folding of planar patterned membranes, provide a promising means to solve this problem. Here, we investigate self-assembly processes driven by wetting interactions to shape the contour of a functional, nonplanar photovoltaic (PV) device. A mechanics model based on the theory of thin plates is developed to identify the critical conditions for self-folding of different 2D geometrical shapes. This strategy is demonstrated for specifically designed millimeter-scale silicon objects, which are self-assembled into spherical, and other 3D shapes and integrated into fully functional light-trapping PV devices. The resulting 3D devices offer a promising way to efficiently harvest solar energy in thin cells using concentrator microarrays that function without active light tracking systems.

Photonic guiding structures in lithium niobate crystals produced by energetic ion beams

Abstract: A range of ion beam techniques have been used to fabricate a variety of photonic guiding structures in the well-known lithium niobate (LiNbO3 or LN) crystals that are of great importance in integrated photonics/optics. This paper reviews the up-to-date research progress of ion-beam-processed LiNbO3 photonic structures and reports on their fabrication, characterization, and applications. Ion beams are being used with this material in a wide range of techniques, as exemplified by the following examples. Ion beam milling/etching can remove the selected surface regions of LiNbO3 crystals via the sputtering effects. Ion implantation and swift ion irradiation can form optical waveguide structures by modifying the surface refractive indices of the LiNbO3 wafers. Crystal ion slicing has been used to obtain bulk-quality LiNbO3 single-crystalline thin films or membranes by exfoliating the implanted layer from the original substrate. Focused ion beams can either generate small structures of micron or submicron dimen...

Correlating Raman spectral signatures with carrier mobility in epitaxial graphene: a guide to achieving high mobility on the wafer scale.

Abstract: We report a direct correlation between carrier mobility and Raman topography of epitaxial graphene (EG) grown on silicon carbide (SiC). We show the Hall mobility of material on SiC(0001) is highly dependent on thickness and monolayer strain uniformity. Additionally, we achieve high mobility epitaxial graphene (18100 cm(2)/(V s) at room temperature) on SiC(0001) and show that carrier mobility depends strongly on the graphene layer stacking.

Remote plasma processing of interface surfaces

Abstract: Embodiments related to the cleaning of interface surfaces in a semiconductor wafer fabrication process via remote plasma processing are disclosed herein. For example, in one disclosed embodiment, a semiconductor processing apparatus comprises a processing chamber, a load lock coupled to the processing chamber via a transfer port, a wafer pedestal disposed in the load lock and configured to support a wafer in the load lock, and a remote plasma source configured to provide a remote plasma to the load lock.

Ordered arrays of vertically aligned [110] silicon nanowires by suppressing the crystallographically preferred etching directions.

Abstract: The metal-assisted etching direction of Si(110) substrates was found to be dependent upon the morphology of the deposited metal catalyst. The etching direction of a Si(110) substrate was found to be one of the two crystallographically preferred 100 directions in the case of isolated metal particles or a small area metal mesh with nanoholes. In contrast, the etching proceeded in the vertical [110] direction, when the lateral size of the catalytic metal mesh was sufficiently large. Therefore, the direction of etching and the resulting nanostructures obtained by metal-assisted etching can be easily controlled by an appropriate choice of the morphology of the deposited metal catalyst. On the basis of this finding, a generic method was developed for the fabrication of wafer-scale vertically aligned arrays of epitaxial [110] Si nanowires on a Si(110) substrate. The method utilized a thin metal film with an extended array of pores as an etching catalyst based on an ultrathin porous anodic alumina mask, while a prepatterning of the substrate prior to the metal depostion is not necessary. The diameter of Si nanowires can be easily controlled by a combination of the pore diameter of the porous alumina film and varying the thickness of the deposited metal film.

Showerhead and chemical vapor deposition apparatus including the same

Abstract: Provided is a showerhead that can inject a reaction gas into a reaction chamber in a manner such that the injected reaction gas form a spiral vortex flow field. Therefore, the injected reaction gas can be mixed within a shorter distance, and thus the effective deposition radius of a wafer can be increased so that uniform-density deposition can be performed on the entire surface of the wafer using the mixed reaction gas.

CMOS-Analogous Wafer-Scale Nanotube-on-Insulator Approach for Submicrometer Devices and Integrated Circuits Using Aligned Nanotubes

Abstract: Massive aligned carbon nanotubes hold great potential but also face significant integration/assembly challenges for future beyond-silicon nanoelectronics. We report a wafer-scale processing of aligned nanotube devices and integrated circuits, including progress on essential technological components such as wafer-scale synthesis of aligned nanotubes, wafer-scale transfer of nanotubes to silicon wafers, metallic nanotube removal and chemical doping, and defect-tolerant integrated nanotube circuits. We have achieved synthesis of massive aligned nanotubes on complete 4 in. quartz and sapphire substrates, which were then transferred to 4 in. Si/SiO2 wafers. CMOS analogous fabrication was performed to yield transistors and circuits with features down to 0.5 μm, with high current density ∼20 μA/μm and good on/off ratios. In addition, chemical doping has been used to build fully integrated complementary inverter with a gain ∼5, and a defect-tolerant design has been employed for NAND and NOR gates. This full-wafer...

Photographic diagnosis of crystalline silicon solar cells utilizing electroluminescence

Abstract: The photographic surveying of electroluminescence (EL) under forward bias was proved to be a powerful diagnostic tool for investigating not only the material properties but also process induced deficiencies visually in silicon (Si) solar cells. Under forward bias condition, solar cells emit infrared light (wavelength around 1000 to 1200 nm) whose intensity reflects the number of minority carriers in base layers. Thus, all the causes that affect the carrier density can be detected, i.e., the minority carrier diffusion length (or in other words, lifetime), recombination velocity at surfaces and interfaces, etc. (intrinsic material properties), and wafer breakage and electrode breakdown, etc. (extrinsic defects). The EL intensity distribution can be captured by Si CCD camera in less than 1 s, and the detection area simply depends upon the optical lens system suitable to the wide range of 1 cm–1.5 m. This fast and precise technique is superior to the conventional scanning method such as the laser beam induced current (LBIC) method.

Multi-chamber system having compact installation set-up for an etching facility for semiconductor device manufacturing

Abstract: A multi-chamber system of an etching facility for manufacturing semiconductor devices occupies a minimum amount of floor space in a cleanroom by installing a plurality of processing chambers in multi-layers and in parallel along a transfer path situated between the processing chambers. The multi-layers number 2 to 5, and the transfer path can be rectangular in shape and need only be slightly wider than the diameter of a wafer. The total width of the multi-chamber system is the sum of the width of one processing chamber plus the width of the transfer path.

Wafer-scale, sub-5 nm junction formation by monolayer doping and conventional spike annealing.

Abstract: We report the formation of sub-5 nm ultrashallow junctions in 4 in. Si wafers enabled by the molecular monolayer doping of phosphorus and boron atoms and the use of conventional spike annealing. The junctions are characterized by secondary ion mass spectrometry and noncontact sheet resistance measurements. It is found that the majority ( approximately 70%) of the incorporated dopants are electrically active, therefore enabling a low sheet resistance for a given dopant areal dose. The wafer-scale uniformity is investigated and found to be limited by the temperature homogeneity of the spike anneal tool used in the experiments. Notably, minimal junction leakage currents (<1 microA/cm(2)) are observed that highlights the quality of the junctions formed by this process. The results clearly demonstrate the versatility and potency of the monolayer doping approach for enabling controlled, molecular-scale ultrashallow junction formation without introducing defects in the semiconductor.

Use of a biased precoat for reduced first wafer defects in high-density plasma process

Abstract: According to various embodiments, the present teachings include methods for reducing first wafer defects in a high-density plasma chemical vapor deposition process. In an exemplary embodiment, the method can include running a deposition chamber for deposition of film on a first batch of silicon wafers and then cleaning interior surfaces of the deposition chamber. The method can further include inserting a protective electrostatic chuck cover (PEC) wafer on an electrostatic chuck in the deposition chamber and applying power to bias the PEC wafer while simultaneously precoating the deposition chamber with an oxide. The exemplary method can also include re-starting the deposition chamber for deposition of film on a second batch of silicon wafers.

Low temperature plasma-enhanced ALD enables cost-effective spacer defined double patterning (SDDP)

Abstract: The inherent advantages of the Plasma-Enhanced Atomic Layer Deposition (PEALD) technology—excellent conformality and within wafer uniformity, no loading effect—overcome the limitations in this domain of the standard PECVD technique for spacer deposition. The low temperature process capability of PEALD silicon oxide enables direct spacer deposition on photoresist, thus suppressing the need of a patterned template hardmask to design the spacers. By decreasing the number of deposition and patterning steps, this so-called Direct Spacer Defined Double Patterning (DSDDP) integration reduces cost and complexity of the conventional SDDP approach. A successful integration is reported for 32 nm half-pitch polysilicon lines. The performances are promising, especially from the lines, which result from the PEALD spacers: Critical Dimension Uniformity (CDU) of 1.3 nm and Line Width Roughness (LWR) of 2.0 nm.

Damascene write poles produced via full film plating

Abstract: A method for forming a write pole comprises forming a stop layer over a substrate layer of a wafer, the stop layer having an opening above a damascene trench in the substrate layer, and forming a buffer layer over the stop layer, the buffer layer having an opening above the opening of the stop layer. The method further comprises plating a layer of magnetic material over the wafer, disposing a first sacrificial material over a region of the magnetic material above the damascene trench, performing a milling or etching operation over the wafer to remove the magnetic material not covered by the first sacrificial material and to remove the first sacrificial material, disposing a second sacrificial material over the wafer, and performing a polishing operation over the wafer to remove the region of the magnetic material above the damascene trench, the second sacrificial material, and the buffer layer.

Effective surface passivation of crystalline silicon by rf sputtered aluminum oxide

Abstract: In recent years, excellent surface passivation has been achieved on both p-type and n-type surfaces of silicon wafers and solar cells using aluminum oxide deposited by plasma-assisted atomic layer deposition. However, alternative deposition methods may offer practical advantages for large-scale manufacturing of solar cells. In this letter we show that radio-frequency magnetron sputtering is capable of depositing negatively-charged aluminum oxide and achieving good surface passivation both on p-type and n-type silicon wafers. We thus establish that sputtered aluminum oxide is a very promising method for the surface passivation of high efficiency solar cells. (© 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Methods of producing damascene main pole for perpendicular magnetic recording head

Abstract: Methods of producing magnetic recording heads are disclosed. The methods can include providing a wafer comprising a substrate layer in which are disposed a plurality of damascene trenches. The method can further include depositing a pole material across the whole wafer, wherein the plurality of trenches are filled with the pole material. The methods can further include depositing a mask material over the pole material across the whole wafer. The methods can further include performing a first material removal process across the whole wafer to remove the mask material and a first portion of the pole material at a same material removal rate. The methods can further include performing a second material removal process to remove a second portion of the pole material above the substrate layer.

Metrology and 3D reconstruction of devices in a wafer

Abstract: A method for measuring three-dimensional devices in a wafer comprises the step of obtaining a plurality of cross-sectional images of a corresponding plurality of three-dimensional devices in the wafer. The plurality of three-dimensional devices have essentially identical geometries. Each cross-sectional image is obtained from a plane in the corresponding three-dimensional device at a predetermined distance from a fiducial mark thereof. The predetermined distance is different for each of the plurality of cross-sectional images. The method further comprises the step of determining the geometries of the plurality of three-dimensional devices based on the cross-sectional images thereof.

Method for reversibly mounting a device wafer to a carrier substrate

Abstract: New temporary bonding methods and articles formed from those methods are provided. The methods comprise bonding a device wafer to a carrier wafer or substrate only at their outer perimeters in order to assist in protecting the device wafer and its device sites during subsequent processing and handling. The edge bonds formed by this method are chemically and thermally resistant, but can also be softened, dissolved, or mechanically disrupted to allow the wafers to be easily separated with very low forces and at or near room temperature at the appropriate stage in the fabrication process.

Simple approach to wafer-scale self-cleaning antireflective silicon surfaces.

Abstract: A simple approach to wafer-scale self-cleaning antireflective hierarchical silicon structures is demonstrated. By employing the KOH etching and silver catalytic etching, pyramidal hierarchical structures were generated on the crystalline silicon wafer, which exhibit strong antireflection and superhydrophobic properties after fluorination. Furthermore, a flexible superhydrophobic substrate was fabricated by transferring the hierarchical Si structure to the NOA 63 film with UV-assisted imprint lithography. This method is of potential application in optical, optoelectronic, and wettability control devices.

Simple Method for the Covalent Immobilization of Graphene

Abstract: We present a simple and efficient method to immobilize graphene on silicon wafers using perfluorophenylazide (PFPA) as the coupling agent. Graphene sheets were covalently attached to PFPA-functionalized wafer surface by a simple heat treatment under ambient conditions. The formation of single and multiple layers of graphene were confirmed by Raman spectroscopy and optical and atomic force microscopy. Evidence of covalent bond formation between graphene and PFPA decorated silicon wafer was given by X-ray photoelectron spectroscopy and sonication treatment.

Silicon nanowire transistor with a channel width of 4 nm fabricated by atomic force microscope nanolithography

Abstract: The emergence of an ultrasensitive sensor technology based on silicon nanowires requires both the fabrication of nanoscale diameter wires and the integration with microelectronic processes. Here we demonstrate an atomic force microscopy lithography that enables the reproducible fabrication of complex single-crystalline silicon nanowire field-effect transistors with a high electrical performance. The nanowires have been carved from a silicon-on-insulator wafer by a combination of local oxidation processes with a force microscope and etching steps. We have fabricated and measured the electrical properties of a silicon nanowire transistor with a channel width of 4 nm. The flexibility of the nanofabrication process is illustrated by showing the electrical performance of two nanowire circuits with different geometries. The fabrication method is compatible with standard Si CMOS processing technologies and, therefore, can be used to develop a wide range of architectures and new microelectronic devices.