Showing papers on "Wafer published in 2010"

100-GHz Transistors from Wafer-Scale Epitaxial Graphene

Abstract: The high carrier mobility of graphene has been exploited in field-effect transistors that operate at high frequencies. Transistors were fabricated on epitaxial graphene synthesized on the silicon face of a silicon carbide wafer, achieving a cutoff frequency of 100 gigahertz for a gate length of 240 nanometers. The high-frequency performance of these epitaxial graphene transistors exceeds that of state-of-the-art silicon transistors of the same gate length.

Enhanced absorption and carrier collection in Si wire arrays for photovoltaic applications

Abstract: The use of silicon nanostructures in solar cells offers a number of benefits, such as the fact they can be used on flexible substrates. A silicon wire-array structure, containing reflecting nanoparticles for enhanced absorption, is now shown to achieve 96% peak absorption efficiency, capturing 85% of light with only 1% of the silicon used in comparable commercial cells. Si wire arrays are a promising architecture for solar-energy-harvesting applications, and may offer a mechanically flexible alternative to Si wafers for photovoltaics1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17. To achieve competitive conversion efficiencies, the wires must absorb sunlight over a broad range of wavelengths and incidence angles, despite occupying only a modest fraction of the array’s volume. Here, we show that arrays having less than 5% areal fraction of wires can achieve up to 96% peak absorption, and that they can absorb up to 85% of day-integrated, above-bandgap direct sunlight. In fact, these arrays show enhanced near-infrared absorption, which allows their overall sunlight absorption to exceed the ray-optics light-trapping absorption limit18 for an equivalent volume of randomly textured planar Si, over a broad range of incidence angles. We furthermore demonstrate that the light absorbed by Si wire arrays can be collected with a peak external quantum efficiency of 0.89, and that they show broadband, near-unity internal quantum efficiency for carrier collection through a radial semiconductor/liquid junction at the surface of each wire. The observed absorption enhancement and collection efficiency enable a cell geometry that not only uses 1/100th the material of traditional wafer-based devices, but also may offer increased photovoltaic efficiency owing to an effective optical concentration of up to 20 times.

Wafer-Scale Synthesis and Transfer of Graphene Films

Abstract: We developed means to produce wafer scale, high-quality graphene films as large as 3 in. wafer size on Ni and Cu films under ambient pressure and transfer them onto arbitrary substrates through instantaneous etching of metal layers. We also demonstrated the applications of the large-area graphene films for the batch fabrication of field-effect transistor (FET) arrays and stretchable strain gauges showing extraordinary performances. Transistors showed the hole and electron mobilities of the device of 1100 ± 70 and 550 ± 50 cm2/(V s) at drain bias of −0.75 V, respectively. The piezo-resistance gauge factor of strain sensor was ∼6.1. These methods represent a significant step toward the realization of graphene devices in wafer scale as well as application in optoelectronics, flexible and stretchable electronics.

GaAs photovoltaics and optoelectronics using releasable multilayer epitaxial assemblies

Abstract: Although compound semiconductors like gallium arsenide have a substantial performance advantage over silicon in photovoltaic and optoelectronic applications, these do not outweigh the costly process of growing large, high-quality layers of these materials and transferring them to flexible or transparent substrates for use in devices such as solar cells, night vision cameras and wireless communication systems. But now John Rogers and his team demonstrate a new fabrication approach that may remove this disadvantage. They grow films of GaAs and AlGaAs in thick, multilayered assemblies in a single deposition sequence, then release the individual layers and distribute them over foreign substrates by printing. The technological potential of this strategy to large-area applications is illustrated with the fabrication of GaAs devices such as field-effect transistors on glass and photovoltaic modules on sheets of plastic. Although compound semiconductors like gallium arsenide (GaAs) offer advantages over silicon for photovoltaic and optoelectronic applications, these do not outweigh the costly process of growing large layers of these materials and transferring them to appropriate substrates. However, a new fabrication approach is now demonstrated: films of GaAs and AlGaAs are grown in thick, multilayered assemblies in a single sequence; the individual layers are then released and distributed over foreign substrates by printing. Compound semiconductors like gallium arsenide (GaAs) provide advantages over silicon for many applications, owing to their direct bandgaps and high electron mobilities. Examples range from efficient photovoltaic devices1,2 to radio-frequency electronics3,4 and most forms of optoelectronics5,6. However, growing large, high quality wafers of these materials, and intimately integrating them on silicon or amorphous substrates (such as glass or plastic) is expensive, which restricts their use. Here we describe materials and fabrication concepts that address many of these challenges, through the use of films of GaAs or AlGaAs grown in thick, multilayer epitaxial assemblies, then separated from each other and distributed on foreign substrates by printing. This method yields large quantities of high quality semiconductor material capable of device integration in large area formats, in a manner that also allows the wafer to be reused for additional growths. We demonstrate some capabilities of this approach with three different applications: GaAs-based metal semiconductor field effect transistors and logic gates on plates of glass, near-infrared imaging devices on wafers of silicon, and photovoltaic modules on sheets of plastic. These results illustrate the implementation of compound semiconductors such as GaAs in applications whose cost structures, formats, area coverages or modes of use are incompatible with conventional growth or integration strategies.

Optical Absorption Enhancement in Silicon Nanohole Arrays for Solar Photovoltaics

Abstract: We investigate silicon nanohole arrays as light absorbing structures for solar photovoltaics via simulation. To obtain the same ultimate efficiency as a standard 300 μm crystalline silicon wafer, we find that nanohole arrays require twelve times less silicon by mass. Moreover, our calculations show that nanohole arrays have an efficiency superior to nanorod arrays for practical thicknesses. With well-established fabrication techniques, nanohole arrays have great potential for efficient solar photovoltaics.

Optical constants of graphene measured by spectroscopic ellipsometry

Abstract: A mechanically exfoliated graphene flake ( ? 150×380??m2) on a silicon wafer with 98 nm silicon dioxide on top was scanned with a spectroscopic ellipsometer with a focused spot ( ? 100×55??m2) at an angle of 55°. The spectroscopic ellipsometric data were analyzed with an optical model in which the optical constants were parameterized by B-splines. This parameterization is the key for the simultaneous accurate determination of the optical constants in the wavelength range 210–1000 nm and the thickness of graphene, which was found to be 3.4 A.

Subnanometer Linewidth Uniformity in Silicon Nanophotonic Waveguide Devices Using CMOS Fabrication Technology

Abstract: We report subnanometer linewidth uniformity in silicon nanophotonics devices fabricated using high-volume CMOS fabrication tools. We use wavelength-selective devices such as ring resonators, Mach-Zehnder interferometers, and arrayed waveguide gratings to assess the device nonuniformity within and between chips. The devices were fabricated using 193 or 248 nm optical lithography and dry etching in silicon-on-insulator wafer technology. Using 193 nm optical lithography, we have achieved a linewidth uniformity of 2 nm (after lithography) and 2.6 nm (after dry etch) over 200 mm wafer. Furthermore, with the developed fabrication process, using wavelength-selective devices, we have demonstrated a linewidth control better than 0.6 nm within chip and better than 2 nm chip-to-chip. The necessity for high-resolution optical lithography is demonstrated by comparing device nonuniformity between the 248 and 193 nm optical lithography processes.

Direct Low-Temperature Nanographene CVD Synthesis over a Dielectric Insulator

Abstract: Graphene ranks highly as a possible material for future high-speed and flexible electronics. Current fabrication routes, which rely on metal substrates, require post-synthesis transfer of the graphene onto a Si wafer, or in the case of epitaxial growth on SiC, temperatures above 1000 °C are required. Both the handling difficulty and high temperatures are not best suited to present day silicon technology. We report a facile chemical vapor deposition approach in which nanographene and few-layer nanographene are directly formed over magnesium oxide and can be achieved at temperatures as low as 325 °C.

Direct Low-Temperature Nanographene CVD Synthesis over a Dielectric

Abstract: Graphenerankshighlyasapossiblematerialforfuturehigh-speedandflexibleelectronics.Current fabrication routes, which rely on metal substrates, require post-synthesis transfer of the graphene onto a Si wafer, or in the case of epitaxial growth on SiC, temperatures above 1000 °C are required. Both the handling difficultyandhightemperaturesarenotbestsuitedtopresentdaysilicontechnology.Wereportafacilechemical vapor deposition approach in which nanographene and few-layer nanographene are directly formed over magnesium oxide and can be achieved at temperatures as low as 325 °C.

Wafer-scale synthesis of graphene by chemical vapor deposition and its application in hydrogen sensing

Abstract: Graphene with a large area was synthesized on Cu foils by chemical vapor deposition under ambient pressure. A 4 �� × 4 �� graphene film was transferred onto a 6 �� Si wafer with a thermally grown oxide film. Raman mapping indicates monolayer graphene dominates the transferred graphene film. Gas sensors were fabricated on a 4 mm × 3 mm size graphene film with a 1 nm palladium film deposited for hydrogen detection. Hydrogen in air with concentrations in 0.0025-1% (25-10,000 ppm) was used to test graphene- based gas sensors. The gas sensors based on palladium-decorated graphene films show high sensitivity, fast response and recovery, and can be used with multiple cycles. The mechanism of hydrogen detection is also discussed.

A strong antireflective solar cell prepared by tapering silicon nanowires.

Abstract: Vertically aligned silicon nanowires (SiNWs) were cost-effectively formed on a four-inch silicon wafer using a simple room temperature approach, i.e., metal-assisted electroless etching. Tapering the NWs by post-KOH dipping achieved separation of each NW from the bunched NW, resulting in a strong enhancement of broadband optical absorption. As electroless etching time increases, the optical crossover feature was observed in the tradeoff between enhanced light trapping (by graded-refractive index during initial tapering) and deteriorated reflectance (by decreasing the areal density of NWs during later tapering). Compared to the bunched SiNWs, tapered NW solar cells demonstrated superior photovoltaic characteristics, such as a short circuit current of 17.67 mA/cm² and a cell conversion efficiency of ~6.56% under 1.5 AM illumination.

Highly uniform 300 mm wafer-scale deposition of single and multilayered chemically derived graphene thin films.

Abstract: The deposition of atomically thin highly uniform chemically derived graphene (CDG) films on 300 mm SiO(2)/Si wafers is reported. We demonstrate that the very thin films can be lifted off to form uniform membranes that can be free-standing or transferred onto any substrate. Detailed maps of thickness using Raman spectroscopy and atomic force microscopy height profiles reveal that the film thickness is very uniform and highly controllable, ranging from 1-2 layers up to 30 layers. After reduction using a variety of methods, the CDG films are transparent and electrically active with FET devices yielding high mobilities of approximately 15 cm(2)/(V s) and sheet resistance of approximately 1 kOmega/sq at approximately 70% transparency.

Direct measurement of graphene adhesion on silicon surface by intercalation of nanoparticles

Abstract: We report a technique to characterize adhesion of monolayered/multilayered graphene sheets on silicon wafer. Nanoparticles trapped at graphene-silicon interface act as point wedges to support axisymmetric blisters. Local adhesion strength is found by measuring the particle height and blister radius using a scanning electron microscope. Adhesion energy of the typical graphene-silicon interface is measured to be 151±28 mJ/m2. The proposed method and our measurements provide insights in fabrication and reliability of microelectromechanical/nanoelectromechanical systems.

Through-wafer interconnects for photoimager and memory wafers

Abstract: A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.

Silicon photonics manufacturing.

Abstract: Most demonstrations in silicon photonics are done with single devices that are targeted for use in future systems. One of the costs of operating multiple devices concurrently on a chip in a system application is the power needed to properly space resonant device frequencies on a system's frequency grid. We asses this power requirement by quantifying the source and impact of process induced resonant frequency variation for microdisk resonators across individual die, entire wafers and wafer lots for separate process runs. Additionally we introduce a new technique, utilizing the Transverse Electric (TE) and Transverse Magnetic (TM) modes in microdisks, to extract thickness and width variations across wafers and dice. Through our analysis we find that a standard six inch Silicon on Insulator (SOI) 0.35 μm process controls microdisk resonant frequencies for the TE fundamental resonances to within 1 THz across a wafer and 105 GHz within a single die. Based on demonstrated thermal tuner technology, a stable manufacturing process exhibiting this level of variation can limit the resonance trimming power per resonant device to 231 μW. Taken in conjunction with the power to compensate for thermal environmental variations, the expected power requirement to compensate for fabrication-induced non-uniformities is 17% of that total. This leads to the prediction that thermal tuning efficiency is likely to have the most dominant impact on the overall power budget of silicon photonics resonator technology.

Wafer-Scale High-Throughput Ordered Growth of Vertically Aligned ZnO Nanowire Arrays

Abstract: This article presents an effective approach for patterned growth of vertically aligned ZnO nanowire (NW) arrays with high throughput and low cost at wafer scale without using cleanroom technology. Periodic hole patterns are generated using laser interference lithography on substrates coated with the photoresist SU-8. ZnO NWs are selectively grown through the holes via a low-temperature hydrothermal method without using a catalyst and with a superior control over orientation, location/density, and as-synthesized morphology. The development of textured ZnO seed layers for replacing single crystalline GaN and ZnO substrates extends the large-scale fabrication of vertically aligned ZnO NW arrays on substrates of other materials, such as polymers, Si, and glass. This combined approach demonstrates a novel method of manufacturing large-scale patterned one-dimensional nanostructures on various substrates for applications in energy harvesting, sensing, optoelectronics, and electronic devices.

Accommodating device for retaining wafers

Abstract: A receiving means for receiving and mounting of wafers, comprised of a mounting surface, mounting means for mounting a wafer onto the mounting surface and compensation means for active, locally controllable, compensation of local and/or global distortions of the wafer.

Film deposition apparatus, film deposition method, and computer readable storage medium

Abstract: A rotation table on which a wafer is placed is rotated around a vertical axis in order to supply to an upper surface of the wafer a first reaction gas for allowing the first reaction gas to be adsorbed on the upper surface, an auxiliary gas that reacts with the first reaction gas to produce an intermediate product having reflowability, and a second reaction gas that is reacted with the intermediate product to produce a reaction product in this order; and the reaction product is heated by a heating lamp in order to densify the reaction product.

Fabrication of porogen residues free and mechanically robust low-k materials

Abstract: A method is provided for producing a porogen-residue-free ultra low-k film with porosity higher than 50% and a high elastic modulus above 5 GPa. The method starts with depositing a SiCOH film using Plasma Enhanced Chemical Vapor Deposition (PE-CVD) or Chemical Vapor Deposition (CVD) onto a substrate and then first Performing an atomic hydrogen treatment at elevated wafer temperature in the range of 200° C. up to 350° C. to remove all the porogens and then performing a UV assisted thermal curing step.

Processing device, electrode, electrode plate, and processing method

Abstract: A processing gas fed from a gas feed pipe (8) through a gas introducing port (9) flows first into an outer annular gas flow channel (20 a), where it is circumferentially diffused, and then into an inner annular gas flow channel (20 b) via a passageway (23), and from this inner annular gas flow channel (20 b) it flows into a gas diffusion gap (7) in the back surface of a shower head (6) via a gas feed hole 25. Thereafter, the processing gas is diffused in the gas diffusion gap (7) and delivered from gas delivery holes (5) to a semiconductor wafer (W). This makes it possible to improve the uniformity of in-plane process, as compared with the prior art, and to make a uniform process.

Top-Gated Epitaxial Graphene FETs on Si-Face SiC Wafers With a Peak Transconductance of 600 mS/mm

Abstract: In this letter, we present state-of-the-art performance of top-gated graphene n-FETs and p-FETs fabricated with epitaxial graphene layers grown on Si-face 6H-SiC substrates on 50-mm wafers. The current-voltage characteristics of these devices show excellent saturation with on-state current densities (Ion) of 0.59 A/mm at Vds = 1 V and 1.65 A/mm at Vds = 3 V. Ion/Ioff ratios of 12 and 19 were measured at Vds = 1 and 0.5 V, respectively. A peak extrinsic gm as high as 600 mS/mm was measured at Vds = 3.05 V, with a gate length of 2.94 ?m. The field-effect mobility versus effective electric field (Eeff) was measured for the first time in epitaxial graphene FETs, where record field-effect mobilities of 6000 cm2/V·s for electrons and 3200 cm2/V·s for holes were obtained at Eeff ~ 0.27 MV/cm .

Wafer-scale synthesis of single-crystal zigzag silicon nanowire arrays with controlled turning angles.

Abstract: Silicon nanowires (SiNWs) having curved structures may have unique advantages in device fabrication. However, no methods are available to prepare curved SiNWs controllably. In this work, we report the preparation of three types of single-crystal SiNWs with various turning angles via metal-assisted chemical etching using (111)-oriented silicon wafers near room temperature. The zigzag SiNWs are single crystals and can be p- or n-doped using corresponding Si wafer as substrate. The controlled growth direction is attributed to the preferred movement of Ag nanoparticles along ⟨001⟩ and other directions in Si wafer. Our results demonstrate that metal-assisted chemical etching may be a viable approach to fabricate SiNWs with desired turning angles by utilizing the various crystalline directions in a Si wafer.

Semiconductor die singulation method

Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer by etching openings completely through the semiconductor wafer.

Silicon Porosification: State of the Art

Abstract: This review is devoted to the analysis of the problems related to fabrication of the Si porous layers. The review was motivated by a great interest to Si-based porous materials from nano- to macro-scale for various applications in electronics, optoelectronics, photonics, chemical sensors, biosensors, etc. The peculiarities of the silicon porosification and the principles of preparing porous layers are considered in the present article. Various methods used for Si porosification such as chemical stain etching, chemical vapor etching, laser-induced etching, metal-assisted etching, spark processing and reactive ion (plasma) etching were analyzed. However, the main attention was focused on electrochemical porosification of Si. The review discusses in detail the influence of parameters such as electrolyte composition and pH, current density, etching time, temperature, wafer doping and orientation, lighting, magnetic field, and ultrasonic agitation on the process of Si porosification. It was shown that the stru...

Embedded Wafer Level Ball Grid Array (eWLB)

Abstract: The main challenges of today's device packaging are miniaturization, continuously increasing operating frequencies/high data rates, high number of I/Os, reliability, and thermal requirements One of the major package trends driven by mobile-phone applications is the Wafer Level Ball Grid Array (WLB) Drivers for the implementation of WLB technology are cost reduction, smaller form factor and better electrical performance with respect to high frequency applications Thin-film WLB technology consists in realizing additional redistribution layers above the passivation of a semiconductor chip using standard thin-film techniques to rearrange peripheral pads on the wafer in an array pattern A hard limit will be reached with this technology, when the number of I/Os reaches a larger number dian can be fitted on the silicon chip at a given pitch We introduce Infineon's embedded Wafer Level Ball Grid Array technology, which allows fitting interconnects onto a so-called fan-out area extending the chip area The core process of this emerging technology is the encapsulation of silicon dice by compression molding The eWLB technology is a forward-looking development of the WLB technology, upholding the known benefits such as small package dimensions, excellent electrical and thermal performance, and maximum connection density However, this technology significantly increases the functionality and application spread Due to eWLB complex semiconductor chips such as modem and processor chips for applications in mobile communications require a high number of solder connections with standardized contact spacing to be produced with a minimal footprint At the same time, the packages can be provided with as many solder contacts as needed The possibility of additional wiring area around the chip proper means that the wafer-level packaging technology also lends itself to new space-sensitive applications We demonstrate the capabilities of Infineon's molded embedded Wafer Level Package Technology and show how we extended it towards a Platform Technology The qualified Platform we introduce here covers currently a range of package sizes up to 8×8mm2 at a ball pitch of 05mm The Qualification Criteria we have applied follow the tests described in JEDEC Standard Number 26-A

Heterogeneous Integration of Compound Semiconductors

Abstract: The ability to tailor compound semiconductors and to integrate them onto foreign substrates can lead to superior or novel functionalities with a potential impact on various areas in electronics, optoelectronics, spintronics, biosensing, and photovoltaics. This review provides a brief description of different approaches to achieve this heterogeneous integration, with an emphasis on the ion-cut process, also known commercially as the Smart-Cut TM process. This process combines semiconductor wafer bonding and undercutting using defect engineering by light ion implantation. Bulk-quality heterostructures frequently unattainable by direct epitaxial growth can be produced, provided that a list of technical criteria is fulfilled, thus offering an additional degree of freedom in the design and fabrication of heterogeneous and flexible devices. Ion cutting is a generic process that can be employed to split and transfer fine monocrystalline layers from various crystals. Materials and engineering issues as well as our current understanding of the underlying physics involved in its application to cleaving thin layers from freestanding GaN, InP, and GaAs wafers are presented.