Showing papers on "Wafer published in 2012"

Wafer-Scale MoS2 Thin Layers Prepared by MoO3 Sulfurization

Abstract: Atomically thin molybdenum disulfide (MoS2) layers have attracted great interest due to their direct-gap property and potential applications in optoelectronics and energy harvesting. Meanwhile, they are extremely bendable, promising for applications in flexible electronics. However, the synthetic approach to obtain large-area MoS2 atomic thin layers is still lacking. Here we report that wafer-scale MoS2 thin layers can be obtained using MoO3 thin films as a starting material followed by a two-step thermal process, reduction of MoO3 at 500 °C in hydrogen and sulfurization at 1000 °C in the presence of sulfur. Spectroscopic, optical and electrical characterizations reveal that these films are polycrystalline and with semiconductor properties. The obtained MoS2 films are uniform in thickness and easily transferable to arbitrary substrates, which make such films suitable for flexible electronics or optoelectronics.

Lithium niobate on insulator (LNOI) for micro-photonic devices

Abstract: The state-of-the-art of high-refractive-index-contrast single-crystalline thin lithium niobate (LiNbO3) films as a new platform for high-density integrated optics is reviewed. Sub-micrometer thin LiNbO3 films are obtained by “ion-slicing”. They can be bonded by two different techniques to a low-index substrate to obtain “lithium niobate on insulator” (LNOI) even as wafer of 3” diameter. Different micro- and nano-structuring techniques have been used to successfully develop micro-photonic devices. To be specific, the fabrication and characterization of LNOI photonic wires with cross-section < 1 µm2, periodically poled LNOI photonic wires for second harmonic generation, electro-optically tunable microring resonators, free standing microrings for hybrid integration, and photonic crystal structures are described.

Efficient light trapping in inverted nanopyramid thin crystalline silicon membranes for solar cell applications.

Abstract: Thin-film crystalline silicon (c-Si) solar cells with light-trapping structures can enhance light absorption within the semiconductor absorber layer and reduce material usage. Here we demonstrate that an inverted nanopyramid light-trapping scheme for c-Si thin films, fabricated at wafer scale via a low-cost wet etching process, significantly enhances absorption within the c-Si layer. A broadband enhancement in absorptance that approaches the Yablonovitch limit (Yablonovitch, E. J. Opt. Soc. Am.1987, 72, 899–907 ) is achieved with minimal angle dependence. We also show that c-Si films less than 10 μm in thickness can achieve absorptance values comparable to that of planar c-Si wafers thicker than 300 μm, amounting to an over 30-fold reduction in material usage. Furthermore the surface area increases by a factor of only 1.7, which limits surface recombination losses in comparison with other nanostructured light-trapping schemes. These structures will not only significantly curtail both the material and proc...

19%‐efficient and 43 µm‐thick crystalline Si solar cell from layer transfer using porous silicon

Abstract: We present a both-sides-contacted thin-film crystalline silicon (c-Si) solar cell with a confirmed AM1.5 efficiency of 19.1% using the porous silicon layer transfer process. The aperture area of the cell is 3.98 cm2. This is the highest efficiency ever reported for transferred Si cells. The efficiency improvement over the prior state of the art (16.9%) is achieved by implementing recent developments for Si wafer cells such as surface passivation with aluminum oxide and laser ablation for contacting. The cell has a short-circuit current density of 37.8 mA cm−2, an open-circuit voltage of 650 mV, and a fill factor of 77.6%. Copyright © 2011 John Wiley & Sons, Ltd.

Kinetics of initial lithiation of crystalline silicon electrodes of lithium-ion batteries.

Abstract: Electrochemical experiments were conducted on {100}, {110}, and {111} silicon wafers to characterize the kinetics of the initial lithiation of crystalline Si electrodes. Under constant current conditions, we observed constant cell potentials for all orientations, indicating the existence of a phase boundary that separates crystalline silicon from the amorphous lithiated phase. For a given potential, the velocity of this boundary was found to be faster for {110} silicon than for the other two orientations. We show that our measurements of varying phase boundary velocities can accurately account for anisotropic morphologies and fracture developed in crystalline silicon nanopillars. We also present a kinetic model by considering the redox reaction at the electrolyte/lithiated silicon interface, diffusion of lithium through the lithiated phase, and the chemical reaction at the lithiated silicon/crystalline silicon interface. From this model, we quantify the rates of the reactions at the interfaces and estimate a lower bound on the diffusivity through the lithiated silicon phase.

Narrow-band waveguide Bragg gratings on SOI wafers with CMOS-compatible fabrication process.

Abstract: We demonstrate the design, fabrication and measurement of integrated Bragg gratings in a compact single-mode silicon-on-insulator ridge waveguide. The gratings are realized by corrugating the sidewalls of the waveguide, either on the ridge or on the slab. The coupling coefficient is varied by changing the corrugation width which allows precise control of the bandwidth and has a high fabrication tolerance. The grating devices are fabricated using a CMOS-compatible process with 193 nm deep ultraviolet lithography. Spectral measurements show bandwidths as narrow as 0.4 nm, which are promising for on-chip applications that require narrow bandwidths such as WDM channel filters. We also present the die-to-die nonuniformity for the grating devices on the wafer, and our analysis shows that the Bragg wavelength deviation is mainly caused by the wafer thickness variation.

Highly Crystalline Soluble Acene Crystal Arrays for Organic Transistors: Mechanism of Crystal Growth During Dip‐Coating

Abstract: The preparation of uniform large-area highly crystalline organic semiconductor thin films that show outstanding carrier mobilities remains a challenge in the field of organic electronics, including organic field-effect transistors. Quantitative control over the drying speed during dip-coating permits optimization of the organic semiconductor film formation, although the kinetics of crystallization at the air–solution–substrate contact line are still not well understood. Here, we report the facile one-step growth of self-aligning, highly crystalline soluble acene crystal arrays that exhibit excellent field-effect mobilities (up to 1.5 cm V−1 s−1) via an optimized dip-coating process. We discover that optimized acene crystals grew at a particular substrate lifting-rate in the presence of low boiling point solvents, such as dichloromethane (b.p. of 40.0 °C) or chloroform (b.p. of 60.4 °C). Variable-temperature dip-coating experiments using various solvents and lift rates are performed to elucidate the crystallization behavior. This bottom-up study of soluble acene crystal growth during dip-coating provides conditions under which one may obtain uniform organic semiconductor crystal arrays with high crystallinity and mobilities over large substrate areas, regardless of the substrate geometry (wafer substrates or cylinder-shaped substrates).

Scaling Hetero-Epitaxy from Layers to Three-Dimensional Crystals

Abstract: Quantum structures made from epitaxial semiconductor layers have revolutionized our understanding of low-dimensional systems and are used for ultrafast transistors, semiconductor lasers, and detectors. Strain induced by different lattice parameters and thermal properties offers additional degrees of freedom for tailoring materials, but often at the expense of dislocation generation, wafer bowing, and cracks. We eliminated these drawbacks by fast, low-temperature epitaxial growth of Ge and SiGe crystals onto micrometer-scale tall pillars etched into Si(001) substrates. Faceted crystals were shown to be strain- and defect-free by x-ray diffraction, electron microscopy, and defect etching. They formed space-filling arrays up to tens of micrometers in height by a mechanism of self-limited lateral growth. The mechanism is explained by reduced surface diffusion and flux shielding by nearest-neighbor crystals.

Research, design and experiment of end effector for wafer transfer robot

Abstract: – Wafer transfer robots play a significant role in IC manufacturing industry and the end effector is an important component of the robots. The purpose of this paper is to improve transfer efficiency of a wafer transfer robot through study of its end effector, and at the same time to reduce wafer deformation., – Finite element method is adopted to analyze wafer deformation. For wafer transfer robot working in vacuum, for the first time, the authors apply the research of microfiber arrays inspired by gecko to the design of robot's end effector, and present equations between robot's transit acceleration and parameters of microfiber arrays. Based on these studies, a kind of micro‐array bump is designed and fixed to a structure optimized end effector. For wafer transfer robot working in atmospheric environment, the authors have analyzed the effects of different factors on wafer deformation. The pressure distributions in absorption area and calculation formula of maximal transfer acceleration are put forward. Finally, a new kind of end effector for atmospheric robot is designed according to these studies., – The experiments results show that transfer efficiency of wafer transfer robot has been significantly improved through application of the research in this paper. Also wafer deformation under absorption force has been controlled., – Through experiments it can be seen that the research in this paper can be used to improve robot transfer ability and decrease wafer deformation in the production environment. Also the studies of end effector lay a solid foundation for further improvement., – This is the first application of the research of gecko‐inspired microfiber arrays to vacuum wafer transfer robot. This paper also carefully analyzes effects of different factors on wafer deformation through finite element method.

Integration of hexagonal boron nitride with quasi-freestanding epitaxial graphene: toward wafer-scale, high-performance devices.

Abstract: Hexagonal boron nitride (h-BN) is a promising dielectric material for graphene-based electronic devices. Here we investigate the potential of h-BN gate dielectrics, grown by chemical vapor deposition (CVD), for integration with quasi-freestanding epitaxial graphene (QFEG). We discuss the large scale growth of h-BN on copper foil via a catalytic thermal CVD process and the subsequent transfer of h-BN to a 75 mm QFEG wafer. X-ray photoelectron spectroscopy (XPS) measurements confirm the absence of h-BN/graphitic domains and indicate that the film is chemically stable throughout the transfer process, while Raman spectroscopy indicates a 42% relaxation of compressive stress following removal of the copper substrate and subsequent transfer of h-BN to QFEG. Despite stress-induced wrinkling observed in the films, Hall effect measurements show little degradation (<10%) in carrier mobility for h-BN coated QFEG. Temperature dependent Hall measurements indicate little contribution from remote surface optical phonon ...

Method and system for performing on-wafer testing of heads

Abstract: A method and system for testing a read transducer are described. The read transducer includes a read sensor fabricated on a wafer. A system includes a test structure that resides on the wafer. The test structure includes a test device and a heater. The test device corresponds to the read sensor. The heater is in proximity to the test device and is configured to heat the test device substantially without heating the read sensor. Thus, the test structure allows for on-wafer testing of the test device at a plurality of temperatures above an ambient temperature.

Effect of Copper TSV Annealing on Via Protrusion for TSV Wafer Fabrication

Abstract: Three-dimensional (3D) integrated circuit (IC) technologies are receiving increasing attention due to their capability to enhance microchip function and performance. While current efforts are focused on the 3D process development, adequate reliability of copper (Cu) through-silicon vias (TSVs) is essential for commercial high-volume manufacturing. Annealing a silicon device with copper TSVs causes high stresses in the copper and may cause a “pumping” phenomenon in which copper is forced out of the blind TSV to form a protrusion. This is a potential threat to the back-end interconnect structure, particularly for low-κ materials, since it can lead to cracking or delamination. In this work, we studied the phenomenon of Cu protrusion and microstructural changes during thermal annealing of a TSV wafer. The extruded Cu-TSV was observed using scanning electron microscopy (SEM), 3D profilometry, and atomic force microscopy (AFM). The electron backscatter diffraction (EBSD) technique was employed to study the grain orientation of Cu-TSV and evolution of the grain size as a function of annealing temperature. The elastic modulus and yield stress of copper were characterized using nanoindentation. A model for Cu protrusion is proposed to provide insight into the failure mechanism. The results help to solve a key TSV-related manufacturing yield and reliability challenge by enabling high-throughput TSV fabrication for 3D IC integration.

Method of making an energy-assisted magnetic recording apparatus

Abstract: A method of making an energy-assisted magnetic recording apparatus is provided. The method comprises the step of aligning a first wafer including a plurality of vertical cavity surface emitting lasers (VCSELs) with a second wafer including a plurality of magnetic recording heads, such that an emitting region of each of the plurality of VCSELs is disposed over a light redirecting structure of a corresponding one of the plurality of magnetic recording heads. The method further comprises the step of bonding the first wafer to the second wafer.

High-Q MEMS Resonators for Laser Beam Scanning Displays

Abstract: This paper reports on design, fabrication and characterization of high-Q MEMS resonators to be used in optical applications like laser displays and LIDAR range sensors. Stacked vertical comb drives for electrostatic actuation of single-axis scanners and biaxial MEMS mirrors were realized in a dual layer polysilicon SOI process. High Q-factors up to 145,000 have been achieved applying wafer level vacuum packaging technology including deposition of titanium thin film getters. The effective reduction of gas damping allows the MEMS actuator to achieve large amplitudes at high oscillation frequencies while driving voltage and power consumption can be minimized. Exemplarily shown is a micro scanner that achieves a total optical scan angle of 86 degrees at a resonant frequency of 30.8 kHz, which fulfills the requirements for HD720 resolution. Furthermore, results of a new wafer based glass-forming technology for fabrication of three dimensionally shaped glass lids with tilted optical windows are presented.

Attachment for substrates having different diameters, substrate processing apparatus, and method of manufacturing substrate or semiconductor device

Abstract: A downsized substrate may be housed in a substrate accommodation vessel (FOUP) constituting a transfer system corresponding to a large diameter substrate. An attachment includes an upper plate and a lower plate supported by a first support groove that can support an 8-inch wafer, and holding columns installed at the upper plate and the lower plate and including a second support groove that can support a 2-inch wafer (if necessary, via a wafer holder and a holder member). Accordingly, the 2-inch wafer can be housed in a pod corresponding to the 8-inch wafer, and the pod, which is a transfer system, can be standardized to reduce cost of a semiconductor manufacturing apparatus. In addition, a distance from each gas supply nozzle to the wafer can be increased to sufficiently mix reactive gases before arrival at the wafer and improve film-forming precision to the wafer.

Roll up nanowire battery from silicon chips

Abstract: Here we report an approach to roll out Li-ion battery components from silicon chips by a continuous and repeatable etch-infiltrate-peel cycle. Vertically aligned silicon nanowires etched from recycled silicon wafers are captured in a polymer matrix that operates as Li+ gel-electrolyte and electrode separator and peeled off to make multiple battery devices out of a single wafer. Porous, electrically interconnected copper nanoshells are conformally deposited around the silicon nanowires to stabilize the electrodes over extended cycles and provide efficient current collection. Using the above developed process we demonstrate an operational full cell 3.4 V lithium-polymer silicon nanowire (LIPOSIL) battery which is mechanically flexible and scalable to large dimensions.

Tailoring the graphene/silicon carbide interface for monolithic wafer-scale electronics

Abstract: The realization of wafer-scale graphene electronics is envisaged to open up the route to the use of graphene in mainstream electronics. Hertel et al. take a step in this direction by fabricating a transistor with a SiC channel and graphene electrodes, with excellent performance up to megahertz frequencies.

Uniform Wafer-Scale Chemical Vapor Deposition of Graphene on Evaporated Cu (111) Film with Quality Comparable to Exfoliated Monolayer

Abstract: This article demonstrated monolayer graphene grown on annealed Cu (111) films on standard oxidized 100-mm Si wafers with higher quality than existing reports. Large area Raman mapping indicated high uniformity (>97% coverage) of monolayer graphene with immeasurable defects (>95% defect-negligible) across the entire wafer. Key to these results is the phase transition of evaporated copper films from amorphous to (111) preferred crystalline, which resulted in subsequent growth of high quality graphene, as corroborated by X-ray diffraction and electron backscatter diffraction. Noticeably, such phase transition of the copper film was observed on a technologically ubiquitous Si wafer with a standard amorphous thermal oxide. A modified two-step etching transfer process was introduced to preserve the clean surface and electrical property of transferred monolayer graphene. The fabricated graphene field effect transistor on a flexible polyimide film achieved peak mobility over 4900 cm2/(V s) at ambient condition.

Low cost and high performance Al nanoparticles for broadband light trapping in Si wafer solar cells

Abstract: In this paper low cost and earth abundant Al nanoparticles are simulated and compared with noble metal nanoparticles Ag and Au for plasmonic light trapping in Si wafer solar cells. It has been found tailored Al nanoparticles enable broadband light trapping leading to a 28.7% photon absorption enhancement in Si wafers, which is much larger than that induced by Ag or Au. Once combined with the SiNx anti-reflection coating, Al nanoparticles can produce a 42.5% enhancement, which is 4.3% higher than the standard SiNx due to the increased absorption in both the blue and near-infrared regions.

Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication

Abstract: Methods of fabricating multi-die assemblies including a wafer segment having no integrated circuitry thereon and having a plurality of vertically stacked dice thereon electrically interconnected by conductive through vias, resulting multi-die assemblies, and semiconductor devices comprising such multi-die assemblies. The wafer segment may function as a heat sink to enhance heat transfer from the stacked dice in the resulting multi-die assembly. The die stacks are fabricated at the wafer level on a base wafer, from which the wafer segment and die stacks are singulated after at least peripheral encapsulation.

Methods and apparatuses for performing wafer level characterization of a plasmon element

Abstract: Improved pump-probe testing methods and apparatuses for measuring the performance of a plasmon element at wafer level are provided In one embodiment, the apparatus includes a light source configured to output a first light beam on a grating located at a first end of a waveguide, the waveguide being configured to couple energy of the first light beam to the plasmon element located at a second end of the waveguide, and an optical probe assembly positioned above a top surface of the wafer The optical probe assembly is configured to direct a second light beam on an area of the wafer including the plasmon element and detect a portion of the second light beam reflected from the area

Towards 20% efficient large-area screen-printed rear-passivated silicon solar cells

Abstract: We have implemented a baseline solar cell process based on today's standard industrially manufactured silicon solar cells. Using this process, we achieve conversion efficiencies up to 18.5% applying 125 × 125 mm² pseudo-square p-type 2–3 Ω cm boron-doped Czochralski silicon wafers featuring screen-printed front and rear contacts and a homogenously doped 70 Ω/□ n+-emitter. Optimizing a print-on-print process for the silver front side metallization, we reduce the finger width from 110 to 70 µm, which increases the conversion efficiency up to 18.9% due to the reduced shadowing loss. In order to further increase the efficiency, we implement two different dielectric rear surface passivation stacks: (i) a silicon dioxide/silicon nitride stack and (ii) an aluminium oxide/silicon nitride stack. The rear contacts to the silicon base are formed by local laser ablation of the passivation stack and aluminium screen printing. The dielectric layer stacks at the rear decrease the surface recombination velocity from Seff,rear = 350 cm/s for a full-area Al back surface field down to Seff,rear = 70 cm/s and increase the internal reflectance from 61% up to 91%. The improved solar cell rear increases the conversion efficiency η up to an independently confirmed value of 19.4%, the short-circuit current density Jsc up to 38.9 mA/cm² and the open-circuit voltage Voc up to 662 mV. The detailed solar cell analysis reveals potential to further increase the conversion efficiency towards 20% in the near future. Copyright © 2011 John Wiley & Sons, Ltd.

Fabrication of flexible and vertical silicon nanowire electronics.

Abstract: Vertical silicon nanowire (SiNW) array devices directly connected on both sides to metallic contacts were fabricated on various non-Si-based substrates (e.g., glass, plastics, and metal foils) in order to fully exploit the nanomaterial properties for final applications. The devices were realized with uniform length Ag-assisted electroless etched SiNW arrays that were detached from their fabrication substrate, typically Si wafers, reattached to arbitrary substrates, and formed with metallic contacts on both sides of the NW array. Electrical characterization of the SiNW array devices exhibits good current–voltage characteristics consistent with the SiNW morphology.

Approach for bonding dies onto interposers

Abstract: A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.

Site Selective Integration of III–V Materials on Si for Nanoscale Logic and Photonic Devices

Abstract: Integrating high electron mobility III–V materials on an existing Si based CMOS processing platform is considered as a main stepping stone to increase the CMOS performance and continue the scaling trend. Owing to the polar nature of III–V materials versus the nonpolar nature of Si, antiphase boundaries (APBs) arise in epitaxially grown III–V materials on Si. Here, we demonstrate an approach to restrict the generation of APBs by selectively depositing a III–V material in narrow Si-trenches as formed within the shallow trench isolation (STI) patterned Si(001) wafers. Based on the detailed crystal structures of Si and III–V materials, a concept has been developed comprising the deposition in “v-grooves” with {111} facets in the Si wafer. The grooves are formed by anisotropic wet etching of Si. When InP is deposited selectively into these “v-grooves”, the crystallographic alignment between the Si and InP restricts the APBs nucleation to the corners of the “v-grooved” trench. This approach offers a promising m...

Handbook of Wafer Bonding

Abstract: TECHNOLOGIES A. Adhesive and Anodic Bonding Glass Frit Wafer Bonding Wafer Bonding Using Spin-On Glass as Bonding Material Polymer Adhesive Wafer Bonding Anodic Bonding B. Direct Wafer Bonding Direct Wafer Bonding Plasma-Activated Bonding C. Metal Bonding Au/Sn Solder Eutectic Au-In Bonding Thermocompression Cu-Cu Bonding of Blanket and Patterned Wafers Wafer-Level Solid-Liquid Interdiffusion Bonding D. Hybrid Metal/Dielectric Bonding Hybrid Metal/Polymer Wafer Bonding Platform Cu/SiO2 Hybrid Bonding Metal/Silicon Oxide Hybrid Bonding APPLICATIONS Microelectromechanical Systems Three-Dimensional Integration Temporary Bonding for Enabling Three-Dimensional Integration and Packaging Temporary Adhesive Bonding with Reconfiguration of Known Good Dies for Three-Dimensional Integrated Systems Thin Wafer Support System for above 250 C Processing and Cold De-bonding Temporary Bonding: Electrostatic