Showing papers on "Wafer published in 2014"

24.7% Record Efficiency HIT Solar Cell on Thin Silicon Wafer

Abstract: A new record conversion efficiency of 24.7% was attained at the research level by using a heterojunction with intrinsic thin-layer structure of practical size (101.8 cm2, total area) at a 98-μm thickness. This is a world height record for any crystalline silicon-based solar cell of practical size (100 cm2 and above). Since we announced our former record of 23.7%, we have continued to reduce recombination losses at the hetero interface between a-Si and c-Si along with cutting down resistive losses by improving the silver paste with lower resistivity and optimization of the thicknesses in a-Si layers. Using a new technology that enables the formation of a-Si layer of even higher quality on the c-Si substrate, while limiting damage to the surface of the substrate, the Voc has been improved from 0.745 to 0.750 V. We also succeeded in improving the fill factor from 0.809 to 0.832.

Wafer-Scale Growth of Single-Crystal Monolayer Graphene on Reusable Hydrogen-Terminated Germanium

Abstract: The uniform growth of single-crystal graphene over wafer-scale areas remains a challenge in the commercial-level manufacturability of various electronic, photonic, mechanical, and other devices based on graphene. Here, we describe wafer-scale growth of wrinkle-free single-crystal monolayer graphene on silicon wafer using a hydrogen-terminated germanium buffer layer. The anisotropic twofold symmetry of the germanium (110) surface allowed unidirectional alignment of multiple seeds, which were merged to uniform single-crystal graphene with predefined orientation. Furthermore, the weak interaction between graphene and underlying hydrogen-terminated germanium surface enabled the facile etch-free dry transfer of graphene and the recycling of the germanium substrate for continual graphene growth.

Wafer bonded four-junction GaInP/GaAs//GaInAsP/GaInAs concentrator solar cells with 44.7% efficiency

Abstract: Triple-junction solar cells from III–V compound semiconductors have thus far delivered the highest solar-electric conversion efficiencies. Increasing the number of junctions generally offers the potential to reach even higher efficiencies, but material quality and the choice of bandgap energies turn out to be even more importance than the number of junctions. Several four-junction solar cell architectures with optimum bandgap combination are found for lattice-mismatched III–V semiconductors as high bandgap materials predominantly possess smaller lattice constant than low bandgap materials. Direct wafer bonding offers a new opportunity to combine such mismatched materials through a permanent, electrically conductive and optically transparent interface. In this work, a GaAs-based top tandem solar cell structure was bonded to an InP-based bottom tandem cell with a difference in lattice constant of 3.7%. The result is a GaInP/GaAs//GaInAsP/GaInAs four-junction solar cell with a new record efficiency of 44.7% at 297-times concentration of the AM1.5d (ASTM G173-03) spectrum. This work demonstrates a successful pathway for reaching highest conversion efficiencies with III–V multi-junction solar cells having four and in the future even more junctions. Copyright © 2014 John Wiley & Sons, Ltd.

Face-to-face transfer of wafer-scale graphene films

Abstract: Graphene has attracted worldwide interest since its experimental discovery, but the preparation of large-area, continuous graphene film on SiO2/Si wafers, free from growth-related morphological defects or transfer-induced cracks and folds, remains a formidable challenge. Growth of graphene by chemical vapour deposition on Cu foils has emerged as a powerful technique owing to its compatibility with industrial-scale roll-to-roll technology. However, the polycrystalline nature and microscopic roughness of Cu foils means that such roll-to-roll transferred films are not devoid of cracks and folds. High-fidelity transfer or direct growth of high-quality graphene films on arbitrary substrates is needed to enable wide-ranging applications in photonics or electronics, which include devices such as optoelectronic modulators, transistors, on-chip biosensors and tunnelling barriers. The direct growth of graphene film on an insulating substrate, such as a SiO2/Si wafer, would be useful for this purpose, but current research efforts remain grounded at the proof-of-concept stage, where only discontinuous, nanometre-sized islands can be obtained. Here we develop a face-to-face transfer method for wafer-scale graphene films that is so far the only known way to accomplish both the growth and transfer steps on one wafer. This spontaneous transfer method relies on nascent gas bubbles and capillary bridges between the graphene film and the underlying substrate during etching of the metal catalyst, which is analogous to the method used by tree frogs to remain attached to submerged leaves. In contrast to the previous wet or dry transfer results, the face-to-face transfer does not have to be done by hand and is compatible with any size and shape of substrate; this approach also enjoys the benefit of a much reduced density of transfer defects compared with the conventional transfer method. Most importantly, the direct growth and spontaneous attachment of graphene on the underlying substrate is amenable to batch processing in a semiconductor production line, and thus will speed up the technological application of graphene.

Molybdenum oxide MoOx: A versatile hole contact for silicon solar cells

Abstract: This letter examines the application of transparent MoOx (x < 3) films deposited by thermal evaporation directly onto crystalline silicon (c-Si) to create hole-conducting contacts for silicon solar cells. The carrier-selectivity of MoOx based contacts on both n- and p-type surfaces is evaluated via simultaneous consideration of the contact recombination parameter J0c and the contact resistivity ρc. Contacts made to p-type wafers and p+ diffused regions achieve optimum ρc values of 1 and 0.2 mΩ·cm2, respectively, and both result in a J0c of ∼200 fA/cm2. These values suggest that significant gains can be made over conventional hole contacts to p-type material. Similar MoOx contacts made to n-type silicon result in higher J0c and ρc with optimum values of ∼300 fA/cm2 and 30 mΩ·cm2 but still offer significant advantages over conventional approaches in terms of contact passivation, optical properties, and device fabrication.

Efficient, compact and low loss thermo-optic phase shifter in silicon

Abstract: We design a resistive heater optimized for efficient and low-loss optical phase modulation in a silicon-on-insulator (SOI) waveguide and characterize the fabricated devices. Modulation is achieved by flowing current perpendicular to a new ridge waveguide geometry. The resistance profile is engineered using different dopant concentrations to obtain localized heat generation and maximize the overlap between the optical mode and the high temperature regions of the structure, while simultaneously minimizing optical loss due to free-carrier absorption. A 61.6 μm long phase shifter was fabricated in a CMOS process with oxide cladding and two metal layers. The device features a phase-shifting efficiency of 24.77 ± 0.43 mW/π and a −3 dB modulation bandwidth of 130.0 ± 5.59 kHz; the insertion loss measured for 21 devices across an 8-inch wafer was only 0.23 ± 0.13 dB. Considering the prospect of densely integrated photonic circuits, we also quantify the separation necessary to isolate thermo-optic devices in the standard 220 nm SOI platform.

Silicon Photonic Integration Platform—Have We Found the Sweet Spot?

Abstract: The current trend in silicon photonics towards higher levels of integration as well as the model of using CMOS foundries for fabrication are leading to a need for standardization of substrate parameters and fabrication processes In particular, for several established research and development foundries that grant general access, silicon-on-insulator wafers with a silicon thickness of 220 nm have become the standard substrate for which devices and circuits have to be designed In this study we investigate the role of silicon device layer thickness in design optimization of various components that need to be integrated in a typical optical transceiver, including both passive ones for routing, wavelength selection, and light coupling as well as active ones such as monolithic modulators and on-chip lasers produced by hybrid integration We find that in all devices considered there is an advantage in using a silicon thickness larger than 220 nm, either for improved performance or for simplified fabrication processes and relaxed tolerances

Photolithographic fabrication of high-performance all-solid-state graphene-based planar micro-supercapacitors with different interdigital fingers

Abstract: Here we demonstrated the fabrication of ultrahigh rate, all-solid-state, planar interdigital graphene-based micro-supercapacitors (MSCs) manufactured by methane plasma-assisted reduction and photolithographic micro-fabrication of graphene oxide films on silicon wafers. Notably, the electrochemical performance of MSCs is significantly enhanced by increasing the number of the interdigital fingers from 8 to 32 and minimizing the finger width from 1175 to 219 μm, highlighting the critical importance of adjusting the number and widths of the fingers in the fabrication of high-performance MSCs. The fabricated graphene-based MSCs delivered an area capacitance of 116 μF cm−2 and a stack capacitance of 25.9 F cm−3. Furthermore, they offered a power density of 1270 W cm−3 that is much higher than that of electrolytic capacitors, an energy density of ∼3.6 mW h cm−3 that is comparable to that of lithium thin-film batteries, and a superior cycling stability of ∼98.5% capacitance retention after 50000 cycles. More importantly, the microdevice can operate well at an ultrahigh scan rate of up to 2000 V s−1, which is three orders of magnitude higher than that of conventional supercapacitors.

Synthesis of wafer-scale uniform molybdenum disulfide films with control over the layer number using a gas phase sulfur precursor

Abstract: We describe a method for synthesizing large-area and uniform molybdenum disulfide films, with control over the layer number, on insulating substrates using a gas phase sulfuric precursor (H2S) and a molybdenum metal source. The metal layer thickness was varied to effectively control the number of layers (2 to 12) present in the synthesized film. The films were grown on wafer-scale Si/SiO2 or quartz substrates and displayed excellent uniformity and a high crystallinity over the entire area. Thin film transistors were prepared using these materials, and the performances of the devices were tested. The devices displayed an on/off current ratio of 105, a mobility of 0.12 cm2 V−1 s−1 (mean mobility value of 0.07 cm2 V−1 s−1), and reliable operation.

Experimental investigation of radiative thermal rectifier using vanadium dioxide

Abstract: Vanadium dioxide (VO2) exhibits a phase-change behavior from the insulating state to the metallic state around 340 K. By using this effect, we experimentally demonstrate a radiative thermal rectifier in the far-field regime with a thin film VO2 deposited on the silicon wafer. A rectification contrast ratio as large as two is accurately obtained by utilizing a one-dimensional steady-state heat flux measurement system. We develop a theoretical model of the thermal rectifier with optical responses of the materials retrieved from the measured mid-infrared reflection spectra, which is cross-checked with experimentally measured heat flux. Furthermore, we tune the operating temperatures by doping the VO2 film with tungsten (W). These results open up prospects in the fields of thermal management and thermal information processing.

GaN-based micro-LED arrays on flexible substrates for optical cochlear implants

Abstract: Currently available cochlear implants are based on electrical stimulation of the spiral ganglion neurons. Optical stimulation with arrays of micro-sized light-emitting diodes (µLEDs) promises to increase the number of distinguishable frequencies. Here, the development of a flexible GaN-based micro-LED array as an optical cochlear implant is reported for application in a mouse model. The fabrication of 15 µm thin and highly flexible devices is enabled by a laser-based layer transfer process of the GaN-LEDs from sapphire to a polyimide-on-silicon carrier wafer. The fabricated 50 × 50 µm2 LEDs are contacted via conducting paths on both p- and n-sides of the LEDs. Up to three separate channels could be addressed. The probes, composed of a linear array of the said µLEDs bonded to the flexible polyimide substrate, are peeled off the carrier wafer and attached to flexible printed circuit boards. Probes with four µLEDs and a width of 230 µm are successfully implanted in the mouse cochlea both in vitro and in vivo. The LEDs emit 60 µW at 1 mA after peel-off, corresponding to a radiant emittance of 6 mW mm−2.

Wafer transfer blade and wafer transfer apparatus having the same

Abstract: A wafer transfer blade including a body including metal oxide and configured to support a wafer, and an adsorbing part on the body, the adsorbing part having at least one therein and configured to apply vacuum pressure to attach the wafer on the body may be provided. The body may include metal oxide to prevent static electricity.

A high electromechanical coupling coefficient SH0 Lamb wave lithium niobate micromechanical resonator and a method for fabrication

Abstract: We present a high coupling coefficient, k eff 2 , micromechanical resonator based on the propagation of SH0 Lamb waves in thin, suspended plates of single crystal X-cut lithium niobate (LiNbO 3 ). The thin plates are fabricated using ion implantation of He to create a damaged layer of LiNbO 3 below the wafer surface. This damaged layer is selectively wet etched in a hydrofluoric (HF) acid based chemistry to form thin, suspended plates of LiNbO 3 without the wafer bonding, layer fracturing and chemical mechanical polishing in previously reported LiNbO 3 microfabrication approaches. The highest coupling coefficient is found for resonators with acoustic propagation rotated 170° from the y -axis, where a fundamental mode SH0 Lamb wave resonator with a plate width of 20 μm and a corresponding resonant frequency of 101 MHz achieves a k eff 2 of 12.4%, a quality factor of 1300 and a resonator figure of merit ( M ) of 185. The k eff 2 and M are among the highest reported for micromechanical resonators.

Direct Light Pattern Integration of Low-Temperature Solution-Processed All-Oxide Flexible Electronics

Abstract: The rise of solution-processed electronics, together with their processing methods and materials, provides unique opportunities to achieve low-cost and low-temperature roll-to-roll printing of non-Si-based devices. Here, we demonstrate a wafer-scale direct light-patterned, fully transparent, all-solution-processed, and layer-by-layer-integrated electronic device. The deep ultraviolet irradiation of specially designed metal oxide gel films can generate fine-patterned shapes of ∼3 μm, which easily manifest their intrinsic properties at low-temperature annealing. This direct light patterning can be easily applied to the 4 in. wafer scale and diverse pattern shapes and provides feasibility for integrated circuit applications through the penetration of the deep ultraviolet range on the quartz mask. With this approach, we successfully fabricate all-oxide-based high-performance transparent thin-film transistors on flexible polymer substrates.

High Coupling Efficiency Etched Facet Tapers in Silicon Waveguides

Abstract: We demonstrate a platform based on etched facet silicon inverse tapers for waveguide-lensed fiber coupling with a loss as low as 0.7 dB/facet. This platform can be fabricated on a wafer scale enabling mass-production of silicon photonic devices with broadband, high-efficiency couplers.

Apparatus and method for transporting wafers between wafer carrier and process tool under vacuum

Abstract: An integrated transport device for a wafer carrier includes: an evacuatable chamber for accommodating therein a wafer carrier having a front opening with a cover; a rotatable platform for placing the wafer carrier thereon in the chamber; and an opening/closing device for opening and closing the cover of the wafer carrier placed on the platform at a first position, wherein the platform rotates to set the wafer carrier at the first position and a second position for transporting a wafer to a wafer-handling chamber.

Electrostatic energy harvesting device with out-of-the-plane gap closing scheme

Abstract: In this paper, we report on an electrostatic energy harvester with an out-of-the-plane gap closing scheme. Using advanced MEMS technology, energy harvesting devices formed by a four wafer stack are batch fabricated and fully packaged at wafer scale. A spin coated CYTOP polymer is used both as an electret material and an adhesive layer for low temperature wafer bonding. The overall size of the device is about 1.1 cm × 1.3 cm. At an external load resistance of 13.4 MΩ, a power output of 0.15 μW is achieved when vibration at an acceleration amplitude of 1 g (∼9.8 m/s2) is applied at a low frequency of 96 Hz. The frequency response of the device is also measured and a broader bandwidth is observed at higher acceleration amplitude.

Enabling Ideal Selective Solar Absorption with 2D Metallic Dielectric Photonic Crystals

Abstract: A metallic dielectric photonic crystal with solar broadband, omni-directional, and tunable selective absorption with high temperature stable (1000 °C, 24 hrs) properties is fabricated on a 6" silicon wafer. The broadband absorption is due to a high density of optical cavity modes overlapped with an anti-reflection coating. Results allow for large-scale, low cost, and efficient solar-thermal energy conversion.

Layered thin film heater and method of fabrication

Abstract: A method of forming thin film heater traces on a wafer chuck includes positioning a pattern, that forms openings corresponding to a desired layout of the heater traces, in proximity to the wafer chuck. The method includes sputtering a material toward the pattern and the wafer chuck such that a portion of the material passes through the openings and adheres to the wafer chuck to form the heater traces. A method of forming thin film heater traces on a wafer chuck includes sputtering a blanket layer of a material onto the wafer chuck, and patterning a photoresist layer utilizing photolithography. The photoresist layer covers the blanket layer in an intended layout of the heater traces, exposing the blanket layer in areas that are not part of the intended layout. The method removes the areas that are not part of the intended layout by etching, and removes the photoresist layer.

Highly Uniform Trilayer Molybdenum Disulfide for Wafer-Scale Device Fabrication

Abstract: Molybdenum disulfide (MoS2) is a layered semiconducting material with a tunable bandgap that is promising for the next generation nanoelectronics as a substitute for graphene or silicon. Despite recent progress, the synthesis of high-quality and highly uniform MoS2 on a large scale is still a challenge. In this work, a temperature-dependent synthesis study of large-area MoS2 by direct sulfurization of evaporated Mo thin films on SiO2 is presented. A variety of physical characterization techniques is employed to investigate the structural quality of the material. The film quality is shown to be similar to geological MoS2, if synthesized at sufficiently high temperatures (1050 °C). In addition, a highly uniform growth of trilayer MoS2 with an unprecedented uniformity of ±0.07 nm over a large area (> 10 cm2) is achieved. These films are used to fabricate field-effect transistors following a straightforward wafer-scale UV lithography process. The intrinsic field-effect mobility is estimated to be about cm2 V–1 s–1 and compared to previous studies. These results represent a significant step towards application of MoS2 in nanoelectronics and sensing.

Silicon carbide photonic crystal cavities with integrated color centers

Abstract: The recent discovery of color centers with optically addressable spin states in 3C silicon carbide (SiC) similar to the negatively charged nitrogen vacancy center in diamond has the potential to enable the integration of defect qubits into established wafer scale device architectures for quantum information and sensing applications. Here, we demonstrate the design, fabrication, and characterization of photonic crystal cavities in 3C SiC films with incorporated ensembles of color centers and quality factor (Q) to mode volume ratios similar to those achieved in diamond. Simulations show that optimized H1 and L3 structures exhibit Q's as high as 45 000 and mode volumes of approximately (λ/n)3. We utilize the internal color centers as a source of broadband excitation to characterize fabricated structures with resonances tuned to the color center zero phonon line and observe Q's in the range of 900–1500 with narrowband photoluminescence collection enhanced by up to a factor of 10. By comparing the Q factors ob...

Comparison of Direct Growth and Wafer Bonding for the Fabrication of GaInP/GaAs Dual-Junction Solar Cells on Silicon

Abstract: Two different process technologies were investigated for the fabrication of high-efficiency GaInP/GaAs dual-junction solar cells on silicon: direct epitaxial growth and layer transfer combined with semiconductor wafer bonding. The intention of this research is to combine the advantages of high efficiencies in III-V tandem solar cells with the low cost of silicon. Direct epitaxial growth of a GaInP/GaAs dual-junction solar cell on a GaAsyP1-y buffer on silicon yielded a 1-sun efficiency of 16.4% (AM1.5g). Threading dislocations that result from the 4% lattice grading are still the main limitation to the device performance. In contrast, similar devices fabricated by semiconductor wafer bonding on n-type inactive Si reached efficiencies of 26.0% (AM1.5g) for a 4-cm2 solar cell device.

Advanced Bulk Defect Passivation for Silicon Solar Cells

Abstract: Through an advanced hydrogenation process that involves controlling and manipulating the hydrogen charge state, substantial increases in the bulk minority carrier lifetime are observed for standard commercial grade boron-doped Czochralski grown silicon wafers from 250-500 μs to 1.3-1.4 ms and from 8 to 550 μs on p-type Czochralski wafers grown from upgraded metallurgical grade silicon. However, the passivation is reversible, whereby the passivated defects can be reactivated during subsequent processes. With appropriate processing that involves controlling the charge state of hydrogen, the passivation can be retained on finished devices yielding independently confirmed voltages on cells fabricated using standard commercial grade boron-doped Czochralski grown silicon over 680 mV. Hence, it appears that the charge state of hydrogen plays an important role in determining the reactivity of the atomic hydrogen and, therefore, ability to passivate defects.

Wafer Scale Synthesis and High Resolution Structural Characterization of Atomically Thin MoS2 Layers

Abstract: Synthesis of atomically thin MoS2 layers and its derivatives with large-area uniformity is an essential step to exploit the advanced properties of MoS2 for their possible applications in electronic and optoelectronic devices In this work, a facile method is reported for the continuous synthesis of atomically thin MoS2 layers at wafer scale through thermolysis of a spin coated-ammonium tetrathiomolybdate film The thickness and surface morphology of the sheets are characterized by atomic force microscopy The optical properties are studied by UV–Visible absorption, Raman and photoluminescence spectroscopies The compositional analysis of the layers is done by X-ray photo­emission spectroscopy The atomic structure and morphology of the grains in the polycrystalline MoS2 atomic layers are examined by high-angle annular dark-field scanning transmission electron microscopy The electron mobilities of the sheets are evaluated using back-gate field-effect transistor configuration The results indicate that this facile method is a promising approach to synthesize MoS2 thin films at the wafer scale and can also be applied to synthesis of WS2 and hybrid MoS2-WS2 thin layers

Large area fabrication of vertical silicon nanowire arrays by silver-assisted single-step chemical etching and their formation kinetics.

Abstract: Vertically aligned silicon nanowire (SiNW) arrays have been fabricated over a large area using a silver-assisted single-step electroless wet chemical etching (EWCE) method, which involves the etching of silicon wafers in aqueous hydrofluoric acid (HF) and silver nitrate (AgNO3) solution. A comprehensive systematic investigation on the influence of different parameters, such as the etching time (up to 15 h), solution temperature (10–80 °C), AgNO3 (5–200 mM) and HF (2–22 M) concentrations, and properties of the multi-crystalline silicon (mc-Si) wafers, is presented to establish a relationship of these parameters with the SiNW morphology. A linear dependence of the NW length on the etch time is obtained even at higher temperature (10–50 °C). The activation energy for the formation of SiNWs on Si(100) has been found to be equal to ~0.51 eV . It has been shown for the first time that the surface area of the Si wafer exposed to the etching solution is an important parameter in determining the etching kinetics in the single-step process. Our results establish that single-step EWCE offers a wide range of parameters by means of which high quality vertical SiNWs can be produced in a very simple and controlled manner. A mechanism for explaining the influence of various parameters on the evolution of the NW structure is discussed. Furthermore, the SiNW arrays have extremely low reflectance (as low as <3% for Si(100) NWs and <12% for mc-Si NWs) compared to ~35% for the polished surface in the 350–1000 nm wavelength range. The remarkably low reflection surface of SiNW arrays has great potential for use as an effective light absorber material in novel photovoltaic architectures, and other optoelectronic and photonic devices.

A 2-in. mosaic wafer made of a single-crystal diamond

Abstract: We synthesized a mosaic diamond wafer 2 in. in size (40 × 60 mm2), which consisted of 24 single-crystal diamond (SCD) plates 10 × 10 mm2 in area, by using microwave plasma chemical vapor deposition. Even by using a cloning technique, cracking frequently occurred and the non-uniformity was remarkable for wafers that were larger than 1 in. in size. This has not been observed in smaller samples before. Appropriate crystallographic directions could avoid the cracking and is one of the predominant factors in fabricating large area SCD wafers. Comparison with numerical simulations highlighted the importance of uniformity of the substrate temperature distribution on the uniformity of the growth.

Toward 300 mm Wafer-Scalable High-Performance Polycrystalline Chemical Vapor Deposited Graphene Transistors

Abstract: The largest applications of high-performance graphene will likely be realized when combined with ubiquitous Si very large scale integrated (VLSI) technology, affording a new portfolio of “back end of the line” devices including graphene radio frequency transistors, heat and transparent conductors, interconnects, mechanical actuators, sensors, and optical devices. To this end, we investigate the scalable growth of polycrystalline graphene through chemical vapor deposition (CVD) and its integration with Si VLSI technology. The large-area Raman mapping on CVD polycrystalline graphene on 150 and 300 mm wafers reveals >95% monolayer uniformity with negligible defects. About 26 000 graphene field-effect transistors were realized, and statistical evaluation indicates a device yield of ∼74% is achieved, 20% higher than previous reports. About 18% of devices show mobility of >3000 cm2/(V s), more than 3 times higher than prior results obtained over the same range from CVD polycrystalline graphene. The peak mobilit...

Experimental Demonstration of 4n2 Classical Absorption Limit in Nanotextured Ultrathin Solar Cells with Dielectric Omnidirectional Back Reflector

Abstract: The experimental demonstration of the 4n2 classical absorption limit in solar cells has been elusive for the last 30 years. Especially the assumptions on front and internal rear reflectance in a slab of absorbing material are not easily fulfilled unless an appropriate light-trapping scheme is applied. We propose an advanced metal-free light-trapping scheme for crystalline silicon wafers. For different bulk thicknesses, at the front side of the wafers we applied a nanotexture known as black-silicon. At the rear side, we implemented a random pyramidal texture coated with a distributed Bragg reflector. Such a dielectric back reflector was designed to exhibit a maximized omnidirectional internal rear reflectance in the region of weak absorption of crystalline silicon. Integrating the measured absorptance spectra of our wafers with the reference solar photon flux between 400 and 1200 nm, we could calculate the so-called implied photogenerated current densities. For wafers thinner than 35 μm, we achieved more t...