Wafer

About: Wafer is a research topic. Over the lifetime, 118092 publications have been published within this topic receiving 1139849 citations.

Dry etching method

Abstract: A dry etching method for etching an aluminum (Al) based layer for effectively combatting the after-corrosion in accordance with three aspects. In the first aspect, while a resist mask and chlorine based gas as known per se are used, S 2 F 2 is used during etching of the barrier metal layer. In this manner, residual chlorine in a carbonaceous polymer as a sidewall protection material or a resist mask is replaced by fluorine, whilst sulfur yielded from S 2 F 2 under conditions of discharge dissociation is deposited to provide for sidewall protection effects. In the second aspect, a SiO 2 mask and an S 2 Cl 2 etching gas are used. Since the sidewall protection material is solely sulfur yielded from S 2 Cl 2 , it becomes possible to avoid the effects of the residual chlorine. In the third aspect, an neutral Ar beam is irradiated at a suitable stage in the etching process for increasing the resistance of the SiO 2 mask against reducing compounds contained in an etching gas for the layer of the aluminum-based material. By irradiation of the neutral beam, a reduction-resistant layer is produced on the surface of the SiO 2 mask to render it possible to reduce the mask thickness without producing problems such as increased step differences on the wafer surface.

Synthesis of Large-Area Silicon Nanowire Arrays via Self-Assembling Nanoelectrochemistry

Abstract: Large-area silicon nanowire arrays have been prepared on a silicon wafer without the use of a template The simple method, which can be carried out near room temperature, involves the nanoelectrochemistry of silver nanowires in an aqueous HF solution containing silver nitrate This technique may be generally applicable to other semiconductors and metals The Figure shows nanodendritic silicon wires

Introduction to microelectronic fabrication

Abstract: (NOTE: Each chapter concludes with Summary, References, and Problems) Preface 1 An Overview of Microelectronic Fabrication A Historical Perspective An Overview of Monolithic Fabrication Processes and Structures Metal-Oxide-Semiconductor (MOS) Processes Basic Bipolar Processing Safety 2 Lithography The Photolithographic Process Etching Techniques Photomask Fabrication Exposure Systems Exposure Sources Optical and Electron Microscopy Further Reading 3 Thermal Oxidation of Silicon The Oxidation Process Modeling Oxidation Factors Influencing Oxidation Rate Dopant Redistribution During Oxidation Masking Properties of Silicon Dioxide Technology of Oxidation Oxide Quality Selective Oxidation and Shallow Trench Formation Oxide Thickness Characterization Process Simulation 4 Diffusion The Diffusion Process Mathematical Model for Diffusion The Diffusion Coefficient Successive Diffusions Solid-Solubility Limits Junction Formation and Characterization Sheet Resistance Generation-Depth and Impurity Profile Measurement Diffusion Simulation Diffusion Systems Gettering 5 Ion Implantation Implantation Technology Mathematical Model for Ion Implantation Selective Implantation Junction Depth and Sheet Resistance Channeling, Lattice Damage, and Annealing Shallow Implantation Source Listing 6 Film Deposition Evaporation Sputtering Chemical Vapor Deposition Epitaxy Further Reading 7 Interconnections and Contacts Interconnections in Integrated Circuits Metal Interconnections and Contact Technology Diffused Interconnections Polysilicon Interconnections and Buried Contacts Silicides and Multilayer-Contact Technology The Liftoff Process Multilevel Metallization Copper Interconnects and Damascene Processes Further Reading 8 Packaging and Yield Testing Wafer Thinning and Die Separation Die Attachment Wire Bonding Packages Flip-Chip and Tape-Automated-Bonding Processes Yield Further Reading 9 MOS Process Integration Basic MOS Device Considerations MOS Transistor Layout and Design Rules Complementary MOS (CMOS) Technology Silicon on Insulator 10 Bipolar Process Integration The Junction-Isolated Structure Current Gain Transit Time Basewidth Breakdown Voltages Other Elements in SBC Technology Layout Considerations Advanced Bipolar Structures Other Bipolar Isolation Techniques BICMOS 11 Processes for Microelectromechanical Systems-MEMS Mechanical Properties of Silicon Bulk Micromachining Silicon Etchants Surface Micromachining High-Aspect-Ratio Micromachining: The LIGA Molding Process Silicon Wafer Bonding IC Process Compatibility Answers to Selected Problems Index

ZnO diode fabricated by excimer-laser doping

Abstract: A ZnO diode was fabricated by using a laser-doping technique to form a p-type ZnO layer on an n-type ZnO substrate. A zinc-phosphide compound, used as a phosphorous source, was deposited on the ZnO wafer and subjected to excimer-laser pulses. The current–voltage characteristics showed a diode characteristic between the phosphorous-doped p-layer and the n-type substrate. Moreover, light emission, with a band-edge component, was observed by forward current injection at 110 K.

Method for manufacturing a semiconductor device

Abstract: A semiconductor wafer, which can be divided into chips at a high yield and a low cost and easily handled during transfer thereof as well, is disclosed. In a semiconductor wafer of such structure that structures with a low mechanical strength, such as suspended microstructures, are exposed at a surface thereof, detachable adhesive sheet making up protective caps for the respective suspended microstructures are formed over the semiconductor wafer. By means of this, even if the semiconductor wafer is diced into the individual chips, respective microstructures on chips are protected from the external force, such as the pressure of cutting water, during the dicing process.