scispace - formally typeset
Topic

Wallace tree

About: Wallace tree is a(n) research topic. Over the lifetime, 378 publication(s) have been published within this topic receiving 3904 citation(s).

...read more

Papers
  More

Journal ArticleDOI: 10.1109/92.238424
J. Fadavi-Ardekani1Institutions (1)
Abstract: The architecture of a design method for an M-bit by N-bit Booth encoded parallel multiplier generator are discussed. An algorithm for reducing the delay inside the branches of the Wallace tree section is explained. The final step of adding two N+or-M-1-bit numbers is done by an optimal carry select adder stage. The algorithm for optimal partitioning of the N+or-M-1-bit adder is also presented. >

...read more

Topics: Wallace tree (64%), Adder (63%), Carry-select adder (63%) ...read more

168 Citations


Proceedings ArticleDOI: 10.1109/ARITH.1987.6158706
18 May 1987-
Abstract: A high speed multiplier and divider for MOS LSI based on a new algorithm is presented. When we implement the multiplier and the divider in LSI, the features such as high speed operation, small number of transistors and easy layout are the most important factors. A computational algorithm using a redundant binary representation has several excellent features such as high speed addition operations. We improved the algorithm and the method of implementation, and designed an advanced multiplier and divider with the above mentioned features. We expect mat our multiplier and divider are excellent compared with multipliers using the Booth algorithm and the Wallace tree, and with divider using the SRT method, respectively.

...read more

Topics: Booth's multiplication algorithm (60%), Multiplier (economics) (59%), Wallace tree (59%) ...read more

159 Citations


Journal ArticleDOI: 10.1109/4.149426
G. Goto1, T. Sato1, M. Nakajima1, T. Sukemura1Institutions (1)
Abstract: A 54-b*54-b parallel multiplier was implemented in 0.88- mu m CMOS using the new, regularly structured tree (RST) design approach. The circuit is basically a Wallace tree, but the tree and the set of partial-product-bit generators are combined into a recurring block which generates seven partial-product bits and compresses them to a pair of bits for the sum and carry signals. This block is used repeatedly to construct an RST block in which even wiring among blocks included in wire shifters is designed as recurring units. By using recurring wire shifters, the authors can expand the level of repeated blocks to cover the entire adder tree, which simplifies the complicated Wallace tree wiring scheme. In addition, to design time savings, layout density is increased by 70% to 6400 transistors/mm/sup 2/, and the multiplication time is decreased by 30% to 13 ns. >

...read more

Topics: Wallace tree (61%), Tree structure (59%)

134 Citations


Journal ArticleDOI: 10.1109/4.18614
M.R. Santoro1, Mark Horowitz1Institutions (1)
Abstract: A 64*64-bit iterating multiplier, the Stanford pipelined iterative multiplier (SPIM), is presented. The pipelined array consists of a small tree of 4:2 adders. The 4:2 tree is better suited than a Wallace tree for a VLSI implementation because it is a more regular structure. A 4:2 carry-save accumulator at the bottom of the array is used to iteratively accumulate partial products, allowing a partial array to be used, which reduces area. SPIM was fabricated in a 1.6- mu m CMOS process. It has a core size of 3.8 mm*6.5 mm and contains 41000 transistors. The on-chip clock generator runs at an internal clock frequency of 85 MHz. The latency for a 64*64-bit fractional multiply is under 120 ns, with a pipeline rate of one multiply every 47 ns. >

...read more

Topics: Clock generator (56%), Wallace tree (56%), Clock rate (53%) ...read more

125 Citations


Proceedings ArticleDOI: 10.1109/ISCAS.1997.608492
F. Kaess1, R. Kanan1, B. Hochet, Michel Declercq1Institutions (1)
09 Jun 1997-
Abstract: A new encoding scheme for high-speed flash analog to digital converters using a Wallace tree is described. It provides a global error filtering and its regular topology optimises the signal propagation. Its application to a 5-bit 1.4-GHz Gallium Arsenide analog-to-digital converter is described.

...read more

Topics: Wallace tree (60%), Flash ADC (59%), Flash (photography) (53%) ...read more

120 Citations


Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202118
202020
201919
201814
201729
201623

Top Attributes

Show by:

Topic's top 5 most impactful authors

Chun Zhang

4 papers, 17 citations

Adly T. Fam

3 papers, 17 citations

Paul Beame

3 papers, 17 citations

Vojin G. Oklobdzija

3 papers, 27 citations

George Varghese

3 papers, 20 citations

Network Information
Related Topics (5)
Adder

24.9K papers, 200.7K citations

77% related
Hardware architecture

10.4K papers, 130.3K citations

76% related
CPU multiplier

7.9K papers, 115.8K citations

75% related
Logic level

7.3K papers, 76.5K citations

74% related
Field-programmable gate array

36K papers, 354.3K citations

74% related