The primary focus of this paper is to discuss the modeling of jitter caused by power supply noise (PSN), named power supply induced jitter (PSIJ). A holistic discussion is presented from the basics of power delivery networks to PSN and eventually to the modeling of PSIJ. The in-depth details and a review of several methodologies available in the literature for the estimation of PSIJ are presented.

A Review on Power Supply Induced Jitter

In this paper, a novel module named time-modulated amplitude-phase weighting with multiple branches (TMAPW-MB) is proposed to realize harmonic beamforming. The harmonic beamforming is then explored to eliminate the conventional digital phase shifters and digital attenuators in antenna arrays. The input and output of general linear frequency modulation (LFM) are investigated in a four-branch TMAPW-MB module. The analysis and numerical results exhibit the attractive capability in the suppression of unwanted harmonic component in radio-frequency (RF) channels. Then, the proposed TMAPW-MB modules are employed in an $X$ -band $1 \times 16$ Vivaldi antenna array for amplitude-phase weighting and, therefore, beamforming. The numerical results show that radiation patterns with −25.0 dB sideband levels (SBLs), −20.0 dB sidelobe levels (SLLs), and ±50° beam scanning range could be realized through the proposed TMAPW-MB module. Meanwhile, due to the removed quantization errors in traditional digital phase shifters and digital attenuators, the proposed module ensures real-time, continuous beam scanning, and precisely controlled SLL and SBL in antenna arrays.

Harmonic Beamforming in Antenna Array With Time-Modulated Amplitude-Phase Weighting Technique

The impedance of the power distribution network (PDN) needs to be minimized in order to prevent unwanted voltage fluctuations at frequencies where current transients occur. To reduce PDN impedance, one can place decoupling capacitors that act as local current sources. However, selecting and placing the right capacitors at the right locations are problematic because of the complexity of modern package and board structures. In addition, decoupling capacitors are not effective at higher frequencies, requiring more complicated techniques such as embedded decoupling. This paper introduces a method of reducing the effort expended by the complex task of decoupling capacitor placement: a genetic algorithm that is customized for the selection and placement of decoupling capacitors. The core engine of this optimizing algorithm is a recently developed technique, the multilayer finite element method (MFEM), which solves for PDN impedances. This paper also highlights a method of incorporating vertical circuit elements into MFEM. Using several test cases, it proves the validity of the inclusion of vertical elements in MFEM and the effectiveness of the optimizer.

Decoupling Capacitor Placement in Power Delivery Networks Using MFEM

A video graphics array (VGA) (640 $\times $ 480) indirect time-of-flight (ToF) CMOS image sensor has been designed with 4-tap 7- $\mu \text{m}$ global-shutter pixel in 65-nm back-side illumination (BSI) process. With a 4-tap pixel structure, we achieved motion artifact-free depth map. Peak current during exposure time has been reduced by current spreading with constant delay chain in the photo-gate driver. Column fixed-pattern phase noise (FPPN) from the constant delay chain is self-compensated by the proposed time-interleaving technique with the two inversely directional clock chains in the photo-gate driver. Quantum efficiency (QE) and demodulation contrast (DC) have been optimized by using appropriate optical engineering techniques with an optimal silicon thickness. As a result, QE of 34% at 940-nm near-infrared and high DC of 86% at 100-MHz modulation frequency have been achieved. In addition, motion artifact and column FPPN are successfully removed in the depth map. The proposed ToF sensor shows depth noise less than 0.57% with 940-nm illuminator over the working distance up to 4 m, and consumes only 160 mW for VGA output at 60 frames/s.

A VGA Indirect Time-of-Flight CMOS Image Sensor With 4-Tap 7- $\mu$ m Global-Shutter Pixel and Fixed-Pattern Phase Noise Self-Compensation

This paper presents an efficient method to estimate jitter in a chain of CMOS inverters in the presence of multiple noise sources, including the power supply noise, input data noise, and the ground bounce noise. For this purpose, necessary noise transfer functions are derived and the recently developed EMPSIJ method is advanced to handle cascaded CMOS inverter stages. Results from the proposed method are compared with the results from a conventional EDA simulator, which demonstrate a significant speed-up using the proposed method for a comparable accuracy.

Efficient Jitter Analysis for a Chain of CMOS Inverters

The #1 Practical Guide to Signal Integrity DesignNow Updated with Extensive New Coverage!This book brings together up-to-the-minute techniques for finding, fixing, and avoiding signal integrity problems in your design. Drawing on his work teaching more than five thousand engineers, world-class signal and power integrity expert Eric Bogatin systematically reviews the root causes of all six families of signal integrity problems and shows how to design them out early in the design cycle. This editions extensive new content includes a brand-new chapter on S-parameters in signal integrity applications, and another on power integrity and power distribution network designtopics at the forefront of contemporary electronics design.Coverage includesA fully up-to-date introduction to signal integrity and physical designHow design and technology selection can make or break the performance of the power distribution networkExploration of key concepts, such as plane impedance, spreading inductance, decoupling capacitors, and capacitor loop inductancePractical techniques for analyzing resistance, capacitance, inductance, and impedanceSolving signal integrity problems via rules of thumb, analytic approximation, numerical simulation, and measurementUnderstanding how interconnect physical design impacts signal integrityManaging differential pairs and lossesHarnessing the full power of S-parameters in high-speed serial link applicationsEnsuring power integrity throughout the entire power distribution pathRealistic design guidelines for improving signal integrity, and much moreUnlike books that concentrate on theoretical derivation and mathematical rigor, this book emphasizes intuitive understanding, practical tools, and engineering discipline. Designed for electronics industry professionals from beginners to experts it will be an invaluable resource for getting signal integrity designs right the first time, every time.

Eric Bogatin

Papers

Signal and Power Integrity - Simplified