Floating-point arithmetic is considered as esoteric subject by many people. This is rather surprising, because floating-point is ubiquitous in computer systems: Almost every language has a floating-point datatype; computers from PCs to supercomputers have floating-point accelerators; most compilers will be called upon to compile floating-point algorithms from time to time; and virtually every operating system must respond to floating-point exceptions such as overflow. This paper presents a tutorial on the aspects of floating-point that have a direct impact on designers of computer systems. It begins with background on floating-point representation and rounding error, continues with a discussion of the IEEE floating point standard, and concludes with examples of how computer system builders can better support floating point.

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What every computer scientist should know about floating-point arithmetic

This paper presents a novel digital feedforward carrier recovery algorithm for arbitrary M-ary quadrature amplitude modulation (M-QAM) constellations in an intradyne coherent optical receiver. The approach does not contain any feedback loop and is therefore highly tolerant against laser phase noise. This is crucial, especially for higher order QAM constellations, which inherently have a smaller phase noise tolerance due to the lower spacing between adjacent constellation points. In addition to the mathematical description of the proposed carrier recovery algorithm also a possible hardware-efficient implementation in a parallelized system is presented and the performance of the algorithm is evaluated by Monte Carlo simulations for square 4-QAM (QPSK), 16-QAM, 64-QAM, and 256-QAM. For the simulations ASE noise and laser phase noise are considered as well as analog-to-digital converter (ADC) and internal resolution effects. For a 1 dB penalty at BER = 10-3, linewidth times symbol duration products of 4.1 x 10-4 (4-QAM), 1.4 x 10-4 (16-QAM), 4.0 x 10-5 (64-QAM) and 8.0 x 10-6 (256-QAM) are tolerable.

Hardware-Efficient Coherent Digital Receiver Concept With Feedforward Carrier Recovery for $M$ -QAM Constellations

The current trend back toward hardware intensive signal processing has uncovered a relative lack of understanding of hardware signal processing architectures. Many hardware efficient algorithms exist, but these are generally not well known due to the dominance of software systems over the past quarter century. Among these algorithms is a set of shift-add algorithms collectively known as CORDIC for computing a wide range of functions including certain trigonometric, hyperbolic, linear and logarithmic functions. While there are numerous articles covering various aspects of CORDIC algorithms, very few survey more than one or two, and even fewer concentrate on implementation in FPGAs. This paper attempts to survey commonly used functions that may be accomplished using a CORDIC architecture, explain how the algorithms work, and explore implementation specific to FPGAs.

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A survey of CORDIC algorithms for FPGA based computers

The main characteristic of Reconfigurable Computing is the presence of hardware that can be reconfigured to implement specific functionality more suitable for specially tailored hardware than on a simple uniprocessor. Reconfigurable computing systems join microprocessors and programmable hardware in order to take advantage of the combined strengths of hardware and software and have been used in applications ranging from embedded systems to high performance computing. Many of the fundamental theories have been identified and used by the Hardware/Software Co-Design research field. Although the same background ideas are shared in both areas, they have different goals and use different approaches.This book is intended as an introduction to the entire range of issues important to reconfigurable computing, using FPGAs as the context, or "computing vehicles" to implement this powerful technology. It will take a reader with a background in the basics of digital design and software programming and provide them with the knowledge needed to be an effective designer or researcher in this rapidly evolving field.

· Treatment of FPGAs as computing vehicles rather than glue-logic or ASIC substitutes
· Views of FPGA programming beyond Verilog/VHDL
· Broad set of case studies demonstrating how to use FPGAs in novel and efficient ways

Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation

Year 2009 marks the completion of 50 years of the invention of CORDIC (coordinate rotation digital computer) by Jack E. Volder. The beauty of CORDIC lies in the fact that by simple shift-add operations, it can perform several computing tasks such as the calculation of trigonometric, hyperbolic and logarithmic functions, real and complex multiplications, division, square-root, solution of linear systems, eigenvalue estimation, singular value decomposition, QR factorization and many others. As a consequence, CORDIC has been utilized for applications in diverse areas such as signal and image processing, communication systems, robotics and 3-D graphics apart from general scientific and technical computation. In this article, we present a brief overview of the key developments in the CORDIC algorithms and architectures along with their potential and upcoming applications.

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50 Years of CORDIC: Algorithms, Architectures, and Applications

This paper describes a single unified algorithm for the calculation of elementary functions including multiplication, division, sin, cos, tan, arctan, sinh, cosh, tanh, arctanh, In, exp and square-root The basis for the algorithm is coordinate rotation in a linear, circular, or hyperbolic coordinate system depending on which function is to be calculated The only operations required are shifting, adding, subtracting and the recall of prestored constants The limited domain of convergence of the algorithm is calculated, leading to a discussion of the modifications required to extend the domain for floating point calculations

J. S. Walther

Papers

A unified algorithm for elementary functions