Frequency-compensation techniques of single-, two- and three-stage amplifiers based on Miller pole splitting and pole-zero cancellation are re-analyzed. The assumptions made, transfer functions, stability criteria, bandwidths, and important design issues of most of the reported topologies are included. Several proposed methods to improve the published topologies are given. In addition, simulations and experimental results are provided to verify the analysis and to prove the effectiveness of the proposed methods.

Analysis of multistage amplifier-frequency compensation

SUMMARY In-building power lines have often been considered as attractive media for high-speed data transmission, particularly for applications like home networking. In this paper, we develop models for power line channels based both on theoretical considerations and practical measurements. We consider power line channel frequency response and noise models in the 1–30 MHz band and propose a number of power line test channels in which to measure the performance of power line modems. Copyright # 2003 John Wiley & Sons, Ltd.

In‐building power lines as high‐speed communication channels: channel characterization and a test channel ensemble

A novel damping-factor-control frequency compensation (DFCFC) technique is presented in this paper with detailed theoretical analysis, This compensation technique improves frequency response, transient response, and power supply rejection for amplifiers, especially when driving large capacitive loads, Moreover, the required compensation capacitors are small and can be easily integrated in commercial CMOS process. Amplifiers using DFCPC and nested Miller compensation (NMC) driving two capacitive loads, 100 and 1000 pF, were fabricated using a 0.8-/spl mu/m CMOS process with V/sub tn/=0.72 V and V/sub tp/=-0.75 V. For the DFCFC amplifier driving a 1000-pF load, a 1-MHz gain-bandwidth product, 51/spl deg/ phase margin, 0.33-V//spl mu/s slew rate, 3.54-/spl mu/s settling time, and 426-/spl mu/W power consumption are obtained with integrated compensation capacitors. Compared to the NMC amplifier, the frequency and transient responses of the DFCFC amplifier are improved by one order of magnitude with insignificant increase of the power consumption.

Three-stage large capacitive load amplifier with damping-factor-control frequency compensation

This paper presents a simple broadband network analyzer technique for measuring balanced loads, such as antennas, without a balun. The technique uses the normal two-port calibration of the network analyzer, which is extended by the addition of two short lengths of cable. From the measured data, a circuit model of the antenna impedances can be found, and both the balanced and unbalanced impedances are readily extracted. Measured and computed data are presented and compared.

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Simple broadband measurements of balanced loads using a network analyzer

This paper presents an efficient algorithm for the transient simulation of multiport distributed interconnect networks in the presence of nonlinear subcircuits. The proposed multilevel multipoint model-reduction algorithm combines the merits of recently proposed Krylov-space techniques and block complex frequency-hopping to generate compact time-domain macromodels. The method overcomes the difficulty of slower transient simulation caused by redundant poles in reduced-order models obtained by Krylov-space methods. Also, it provides an efficient means to translate Krylov-space-based reduced models of distributed/measured networks with frequency-dependent descriptions into time-domain macromodels. In addition, a strategy to preserve the passivity of macromodels during multilevel reduction is presented. An important advantage of the proposed algorithm is that it can directly handle distributed stamps such as transmission lines described by Telegrapher's equations, frequency-dependent parameters, full-wave, and measured subnetworks.

L.O. Chua

Papers

Introduction to circuit synthesis and design