A novel approach to automatic data path synthesis is presented. This approach features innovations in the synthesis process as well as in the system implementation. The synthesis process exhibits three new features. The first relates to a subtask that performs an expert analysis of the input data flow graph and attempts to evenly distribute operations requiring similar resources. This is done using a novel "load balancing" technique. The second consists of a global preselection of operator cells to fulfill an explicit speed constraint. Finally, the third deals with new techniques for register and multiplexer optimization. These features support extended design space search by taking an explicit performance specification into account. The system implementation is based on the LOOPS multiparadigm programming system. In this approach the overall task can be partitioned into complementary subtasks requiring different programming paradigms. These subtasks will be realized using an object-based paradigm, a knowledge-based expert system paradigm, a functional paradigm, or combinations of all three. Two complete examples are given to demonstrate the functionality of the system and to allow comparison with existing systems.

HAL: A Multi-Paradigm Approach to Automatic Data Path Synthesis

This paper describes the design and implementation of a high-level hardware compiler called Flamel. Ordinary Pascal programs are used to define the behavior required of the hardware. Flamel undertakes to find parallelism in the program, so it can produce a fast-running implementation that meets a user-specified cost bound. A number of program transformations create sections of code with more parallel computations than the original program has. A novel feature of Flamel is a method for organizing the search for the transformations that best satisfy the goal. Another new algorithm is one for "expression height reduction": rewriting an ensemble of expressions using algebraic properties in order to compute the expressions faster. An implementation of Flamel has been completed. The output is a description of a datapath and a controller, and at a sufficient level of detail so that good area and execution time figures can be estimated. On a series of tests, Flamel produces implementations of programs that would run 22 to 200 times faster than an MC68000 running the same programs, if the clock cycles were the same. The tests also show that a wide range of time-area tradeoffs are produced by varying the area constraint.

Flamel: A High-Level Hardware Compiler

This paper reports on a new method for using bottom-up design information in the synthesis of integrated circuits from abstract behavioral descriptions. There are two important ways in which this method differs from traditional top-down synthesis techniques. First, it draws on a newly developed procedural database to collect detailed information on the physical and logical properties of the primitives available for building the design. Second, it uses a different method for representing and organizing knowledge about a design that makes possible estimates of physical placement and wiring in the analysis of that design, even at the abstract register-transfer level. This allows a more accurate evaluation of candidate register-transfer designs without doing a full logic-level or transistor-level layout. It also leads to a simple method for systematically exploring the space of possible designs in order to find the one that best meets the designer's objectives and constraints.

Using Bottom-Up Design Techniques in the Synthesis of Digital Hardware from Abstract Behavioral Descriptions

This paper describes behavioral compilation tools built for use in an intelligent silicon compiler. These tools allow the user or an expert system to compile behavioral descriptions to a register transfer level under user-imposed constraints. A flexible design model offers a combination of design features previously unavailable in behavioral compilers such as multicycle, chained, and pipelined function units along with the ability to choose between bus- and mux-based connectivity models. Furthermore, we present a new design strategy that allows easy exploratory design and we describe algorithms for state synthesis and connectivity binding that achieved higher quality designs than previous systems on selected benchmarks. The code for this project is run under 42 BSD Unix on a VAX 11 780 and is written in C.

Design Tools for Intelligent Silicon Compilation

For some time we have been exploring methods of transforming functional specifications into hardware implementations that are suitable for production. The complexity of this task and the potential value have continued to grow with the increasing complexity of processor design and the mounting pressure to shorten machine design times. This paper describes the evolution of the Logic Synthesis System from an experimental tool to a production system for the synthesis of masterslice chip implementations.

The system was used by one project in IBM Poughkeepsie to produce 90 percent of its more than one hundred chip parts. The primary reasons for this success are the use of local transformations to simplify logic representations at several levels of abstraction, and a highly cooperative effort between logic designers and synthesis system designers to understand the logic design process practiced in Poughkeepsie and to incorporate this knowledge into the synthesis system.

LSS: a system for production logic synthesis

S ilrCon collpilat ionl a ncsw techniclue 1'o0 integratecd i.li t CeIsi11 that hats I-CCCIetlV Undercrone initeinsc dcclo0n1vtC scr`t n ns nc cT-iticisni At the imiomenit, therc is ex en disacireeient 0cer ite meaninu ot' the tCi-Ini ''silicOlo tomli at ion itelt'. III t hi a rtielc 'silicon 'onpila tion' williicl'cr to tie antotullat ic sxviIti csis ot' ani ilte-ratced eieLitilIaont tl0o1il0 a c cs-riptioni ot' its behasiot. Tiadoitional otterl-atcclircLuit clesieti tcclniquCs, on the otrher hailndl arc edcpceildld t onl the s lruclure, irait lerthan the hautt 101o out ilic iWttuAtcd . lirtilit. I cour sc, dcsielin is not the onl stcp in thcl roeductioi ofI trsct'l I( '. IFahri atioitand testirte ate also important. III1 ac t, ads anlls it [abr lcation capabilitv hase actualix o01t-ilpped adsaens in cdcsitgnx,wiich is whli dcsien is a Ilopic of' oiih iiiticcst It plrcerilt Sotiic tcstiri isstiues Cde'sIlt ItOrtetabilitV lilCi aILutoiiatic ^cieiration ot' tcst patticrris t'or cxritlpl-arte potentially part ot' the desigJn o)I osCs. CoLIr clut rseat cit is bch itiniig to siow progrcss in tihes arcas alic t hel-e is reasoti to believe t hat silicon rirpiler dedsieitIlIetehodoloex Is iiiore atmcniable to tcst auitonmatioil ii a t iot c i Latidcaif't ccl nietlociso 1-iclel.diparitr bet\\xccnxi t'abrication aridc design is stich} tht x hlllc it isorionaiM to i 'iibI-i caLtcr a moderatclv coriipl\\ citrciilt--oltie thlat is to tb eplicated in pi o-odLcrtio atbo ii 1()()() 00( i Ie it i s iiot ccoiiornie to clesigni suic} a cil-t otili rilses it xxill he replicatecd at least 10,000 tinies .* ib ii ,! malo IC'x-etidorxxil1 riot accept conilillissiois ('ot desitls xiti hout a coltlillit lmerit to a 1000( -Lnit produicti(ir xVolIoIeC. RecLtIeIP tliCe desieSll cost of' an IC' h a l'actolof xxi xxoleCI pr-obahiMx redceC theC tllilliirriiium econoniiiC pnrodctICtioII xolVir1ne to abouIt 1000un)ilts, atici a good i Icor corn itOll hler pa obably Iuccitluc dCsiril cost bh m }ch niot c thall t hat pro b(bl hv a f'actor of' thlree to .sc (see ' i,c-cr I).

Southard

Papers

MacPitts: An Approach to Silicon Compilation