This paper proposes a fast algorithm for computing multiplicative inverses in GF(2 m ) using normal bases. Normal bases have the following useful property: In the case that an element x in GF(2 m ) is represented by normal bases, 2 k power operation of an element x in GF(2 m ) can be carried out by k times cyclic shift of its vector representation. C. C. Wang et al. proposed an algorithm for computing multiplicative inverses using normal bases, which requires ( m − 2) multiplications in GF(2 m ) and ( m − 1) cyclic shifts. The fast algorithm proposed in this paper also uses normal bases, and computes multiplicative inverses iterating multiplications in GF(2 m ). It requires at most 2[log 2 ( m − 1)] multiplications in GF(2 m ) and ( m − 1) cyclic shifts, which are much less than those required in the Wang's method. The same idea of the proposed fast algorithm is applicable to the general power operation in GF(2 m ) and the computation of multiplicative inverses in GF( q m ) ( q = 2 n ).

A fast algorithm for computing multiplicative inverses in GF(2 m ) using normal bases

Optimal normal bases in GF( p n )

Digit-serial architectures are best suited for systems requiring moderate sample rate and where area and power consumption are critical. This paper presents a new approach for designing digit-serial/parallel finite field multipliers. This approach combines both array-type and parallel multiplication algorithms, where the digit-level array-type algorithm minimizes the latency for one multiplication operation and the parallel architecture inside of each digit cell reduces both the cycle-time as well as the switching activities, hence power consumption. By appropriately constraining the feasible primitive polynomials, the mod p(x) operation involved in finite field multiplication can be performed in a more efficient way. As a result, the computation delay and energy consumption of one finite field multiplication using the proposed digit-serial/parallel architectures are significantly less than of those obtained by folding the parallel semi-systolic multipliers. Furthermore, their energy-delay products are reduced by a even larger percentage. Therefore, the proposed digit-serial/parallel architectures are attractive for both low-energy and high-performance applications.

Low-Energy Digit-Serial/Parallel Finite Field Multipliers

This paper presents a configuration of parallel multipliers for GF (2 m ) based on canonical bases. The possible parallel multipliers by the proposed configuration are limited to a class of fields GF (2 m ). However they can be constructed by O(m 2 ) AND-gates and O(m 2 ) EOR-gates with the structural modularity (this is a desirable feature for the hardware implementation), and their operation time is about (log m ) T , where m is the dimension of GF (2 m ) and T is the delay time of an EOR-gate. In order to construct such parallel multipliers, we define two types of polynomials of special form over GF (2), one is called all one polynomial (denoted by AOP) and the other is called equally spaced polynomial (denoted by ESP). Furthermore, we show a necessary and sufficient condition for ESPs to be irreducible over GF (2) and the uniqueness of the irreducible ESPs over GF (2). Finally, we propose the configuration of parallel multipliers for a class of fields GF (2 m ) based on irreducible AOPs and ESPs over GF (2).

Structure of parallel multipliers for a class of fields GF(2 m )

We present a new low-complexity bit-parallel canonical basis multiplier for the field GF(2m) generated by an all-one-polynomial. The proposed canonical basis multiplier requires m/sup 2/-1 XOR gates and m/sup 2/ AND gates. We also extend this canonical basis multiplier to obtain a new bit-parallel normal basis multiplier.

Low-complexity bit-parallel canonical and normal basis multipliers for a class of finite fields

Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that can be easily realized on VLSI chips. Massey and Omura [1] recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. In this paper, a pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable, and therefore, naturally suitable for VLSI implementation.

/pdf/vlsi-architectures-for-computing-multiplications-and-180xodb5s8.pdf

Wang

Papers

VLSI Architectures for Computing Multiplications and Inverses in GF(2 m )