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Figure 3: Block Diagram of Implementation Environment: Our design is connected to the rest of the system via (a) non-coherent interface, (b) memorymapped register interface, and (c) coherent cache interface.
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Proceedings Article
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DOI
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A case of system-level hardware/software co-design and co-verification of a commodity multi-processor system with custom hardware
[...]
Sungpack Hong
1
,
Tayo Oguntebi
2
,
Jared Casper
2
,
Nathan Bronson
2
,
Christos Kozyrakis
2
,
Kunle Olukotun
2
- Show less
+2 more
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Institutions (2)
Oracle Corporation
1
,
Stanford University
2
07 Oct 2012
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