Residue Number System (RNS) is a non-weighted number system which was proposed by Garner back in 1959 to achieve fast implementation of addition, subtraction and multiplication operations in special-purpose computations. Unfortunately, RNS did not turn out as a popular alternative to two?s complement number system in those days. The rigidity of instruction set architectures of the market-dominant computers and microprocessors then has been the main barrier to sustain the development of RNS-based applications. In recent years, technological advancement in semiconductor technology has revived the interests to reconsider RNS for application-specific computing. There are at least two unique motivations which make RNS computations more attractive and applicable in modern digital signal processing applications. Firstly, the modular and distributive properties of RNS are used to achieve performance improvements especially in the emerging distributed and ubiquitous computing platforms such as cloud, wireless ad hoc networks, and applications which require tolerance against soft error. Secondly, energy efficiency becomes a key driver in the continual densification of complementary metal oxide semiconductor (CMOS) digital integrated circuits. The high degree of computational parallelism in RNS offers new degree of freedom to optimize energy performance, particularly for very long word length arithmetic such as those involved in the hardware implementation of cryptographic algorithms. Our aim in this paper is to show this revolution by discussing interesting development in RNS and foster the innovative use of RNS for more applications. Different applications of RNS are investigated to demonstrate how this unconventional number system can be leveraged to benefit their implementation.

Residue Number Systems: A New Paradigm to Datapath Optimization for Low-Power and High-Performance Digital Signal Processing Applications

We investigate image and video convolutions based on Fermat number transform (FNT) modulo q=2/sup M/+1 where M is an integer power of two. These transforms are found to be ideal for image convolutions, except that the choices for the word length, restricted by the transform modulus, are rather limited. We discuss two methods to overcome this limitation. First, we allow M to be an arbitrary integer. This gives much wider variety in possible moduli, at the cost of decreased transform length of 16 or 32 points for M<32. Nevertheless, the transform length appears still to be useful especially with block-based image and video filtering applications. We call these transforms the generalized FNT (GFNT). The second solution is to use a residue number system (RNS) to enlarge the effective modulus, while performing actual number theoretic transforms with smaller moduli. This approach appears to be particularly useful with moduli q/sub 1/=2/sup 16/+1 and q/sub 2/=2/sup 8/+1, which allow transforms up to 256 points with a dynamic range of about 24 bits. We design an efficient reconstruction circuit based on mixed radix conversion for converting the result from diminished-1 RNS into normal binary code. The circuit is implemented in VHDL and found to be very small in area. We also discuss the necessary steps in performing convolutions with the GFNT and evaluate the integrated circuit implementation cost for various elementary operations.

Video filtering with Fermat number theoretic transforms using residue number system

Recent papers have reported that the use of residue number coding in digital filters can result in better speed/cost ratios when compared to filters designed with conventional adders and multipliers. This paper presents two approaches to the design of residue-to-analog converters to be used with residue number filters. The first approach, based on the associated mixed radix number system, is particularly useful when it is desired to translate the residue samples directly into analog form. The second approach, based on the Chinese remainder theorem, is a more direct method for translating from residue to weighted binary representation. A hardware feasibility model is described that was constructed to demonstrate the conversion principles.

Techniques for residue-to-analog conversion for residue-encoded digital filters

This paper considers the implementation of a fast Fourier transform (FFT) structure using arrays of read-only memories. The arithmetic operations are based entirely on the residue number system. The most important aspect of the structure relates to the scaling arrays, which are required to prevent overflow. Because of the limitations of the number system, scaling factors have to be chosen on an a priori basis. This paper develops optimum procedures for choosing both scaling factors and the position of scaling arrays in the structure. Some examples are presented relating to the filtering of speech via a convolutional filter structure.

Implementation of FFT structures using the residue number system

In a recent issue of this journal, a hardware implementation of the Chinese Remainder Theorem was proposed for the translation of residue coded outputs into natural integer for an FIR filter realization. The method requires a modulo M adder-shifter network which is not commercially available and has to be constructed from more basic logic elements. This letter presents a more successful technique based on a mixed-radix conversion process. The residue to binary decoder can be built using commercially available elements and requires shorter word lengths in the ROM which stores the output function.

On decoding techniques for residue number system realizations of digital signal processing hardware

In the past, hardware realization of digital signal processing elements have been based upon binary arithmetic concepts. Because of the dependence between digits in binary arithmetic operations, the hardware required to construct arithmetic elements is cumbersome. In the residue number system, arithmetic operations can be performed with complete independence between digits and a corresponding reduction in hardware complexity. In fact, using current technology, arithmetic operations can be carried out using arrays of look-up tables placed in high density ROMs. This paper discusses the application of the residue number system to realizing digital signal processing elements using such arrays and advantages and disadvantages over conventional realizations are discussed. Examples are given of recursive filter and FFT butterfly element realization.

Hardware realization of digital signal processing elements using the residue number system.

Using the Residue Number System (RNS) as a basis for the hardware construction, two different hard-ware structures are discussed for implementing NTTs over a direct sum of Galois Fields GF(m i 2). The first structure uses arrays of read only memories and the second uses arrays of microprocessors; in particular, single chip microprocessors are proposed. The two techniques offer trade offs between speed of operation, and cost. Using the RNS, rather than conventional binary arithmetic, allows more flexibility in the choice of the generator, α, and consequently more flexibility in allowable transform parameters. A selection of parameters, for the two realizations, are discussed when the Galois Field of m i 2elements is a finite field of Gaussian or quadratic integers.

Hardware implementation of convolution using number theoretic transforms

This paper considers an implementation of the FFT based upon the residue number system. This system offers the advantages of using integer based arithmetic operations and a simple hardware realization involving table look-up arrays. The proposed architecture is such that rapid evolutionary changes in read-only-memory technology can be easily incorporated into the hardware realization. In this paper, a generalized expression for predicting RMS relative error that includes A/D quantization, integer normalization and scaling rounding considerations, has been derived. This analysis leads to the optimal choice of several parameters, which are related to error minimization and simplification of the hardware realization. The generalized expression derived with respect to the FFT can also be used to predict errors in high-speed convolution filters.

A. Baraniecka

Papers

Hardware realization of digital signal processing elements using the residue number system.

Hardware implementation of convolution using number theoretic transforms

An error anaylsis of a FFT implementation using the residue number system