http://eia.udg.es/%7Eqsalvi/papers/2006-MJ.pdf

Review of CMOS image sensors

https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=820550

Accuracy vs Efficiency Trade-offs in Optical Flow Algorithms

Analysis of dynamic-range (DR) and signal-to-noise-ratio (SNR) for high fidelity, high-dynamic-range (HDR) image sensor architectures is presented. Four architectures are considered: (i) time-to-saturation, (ii) multiple-capture, (iii) asynchronous self-reset with multiple capture, and (iv) synchronous self-reset with residue readout. The analysis takes into account circuit nonidealities such as quantization noise and the effects of limited pixel area on building block and reference signal performance and accuracy. Examples that demonstrate the behavior of SNR in the extended DR and implementation and power consumption issues for each scheme are presented.

/pdf/quantitative-study-of-high-dynamic-range-image-sensor-48wpj6kvm7.pdf

Quantitative study of high-dynamic-range image sensor architectures

Autonomously operating analog to digital converters are formed into a two dimensional array. The array may incorporate digital signal processing functionality. Such an array is particularly well-suited for operation as a readout integrated circuit and, in combination with a sensor array, forms a digital focal plane array.

Digital readout method and apparatus

This paper presents a digital pixel sensor (DPS) array employing a time domain analogue-to-digital conversion (ADC) technique featuring adaptive dynamic range and programmable pixel response The digital pixel comprises a photodiode, a voltage comparator, and an 8-bit static memory The conversion characteristics of the ADC are determined by an array-based digital control circuit, which linearizes the pixel response, and sets the conversion range The ADC response is adapted to different lighting conditions by setting a single clock frequency Dynamic range compression was also experimentally demonstrated This clearly shows the potential of the proposed technique in overcoming the limited dynamic range typically imposed by the number of bits in a DPS A 64 /spl times/ 64 pixel array prototype was manufactured in a 035-/spl mu/m, five-metal, single poly, CMOS process Measurement results indicate a 100 dB dynamic range, a 41-s mean dark time and an average current of 16 /spl mu/A per DPS

/pdf/a-digital-pixel-sensor-array-with-programmable-dynamic-range-3yzmv620cw.pdf

A digital pixel sensor array with programmable dynamic range

An analog VLSI implementation which mimics the early visual processing stages in insects is described. The system is composed of sixty parallel channels of integrated photodetectors and processing elements. It serves as the front end processor for a motion detection chip. The photodetection circuitry includes p-well junction diodes on a 2 mu m CMOS process and a logarithmic compression to increase the dynamic range of the system. The processing elements consist of an analog differentiator behind each photodetector. The differentiators are low frequency and have been designed using subthreshold design methods. >

An analog implementation of early visual processing in insects

In this paper we propose an on-pixel Analogue-to-Digital Converter (ADC) based on pulse frequency modulation (PFM) scheme. This PFM based converter presents a viable solution for pixel-level based ADC. It uses a simple and robust circuit that can be implemented in a compact area resulting in a 23% fill-factor for a digital vision sensor in 0.25 μm CMOS technology. An in-built light adaptation mechanism has also been implemented which allows the sensor to better adapt to low-light intensity or to adjust the sensor saturation level. As a consequence, the proposed sensor features a programmable dynamic range. Image lag is eliminated since a reset of the photodetector is performed after the conversion period. A prototype comprising a 32 X 32 pixel array has been implemented in CMOS 0.25 μm technology. Each pixel occupies an area of 45 X 45 μm 2 with an average power consumption of 85 μW per pixel.

A vision sensor with on-pixel ADC and in-built light adaptation mechanism

In this paper we investigate important issues in the design of the logarithmic CMOS pixel. In particular, much attention is paid to the optimization of pixel performance in terms of output gain, dynamic range, and fill-factor. In order to increase the gain-bandwidth product, we propose to use the native transistor as source follower. The performance of such a pixel is compared with that of conventional logarithmic pixels. It is shown that the native source follower yields a significant increase in the gain-bandwidth product. In addition, we propose a layout floor-planning strategy which allows us to achieve a 46% fill-factor. In order to compare the performance of the proposed pixel with the conventional NMOS and PMOS logarithmic pixels, a VLSI prototype has been realized using 0.7 /spl mu/m CMOS technology.

A high fill-factor native logarithmic pixel: Simulation, design and layout optimization

A major problem faced by artificial vision systems is the computational bottleneck. The problem can be addressed by incorporating preliminary parallel signal processing in the sensor itself, thereby alleviating subsequent processing requirements. The authors describe a vision system implemented in analog and digital VLSI incorporating sensors and a processing unit. It extracts information such as range, depth and motion of objects in the visual environment. Advantages are its small size and its wide dynamic range which make it very suitable for real-life applications, particularly in robotics.

/pdf/a-micro-sensor-based-on-insect-vision-4bsyf6s1vt.pdf

A. Bouzerdoum

Papers

An analog implementation of early visual processing in insects

A vision sensor with on-pixel ADC and in-built light adaptation mechanism

A vision sensor with on-pixel ADC and in-built light adaptation mechanism

A high fill-factor native logarithmic pixel: Simulation, design and layout optimization

A micro-sensor based on insect vision