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A. Casotto
Researcher at University of California, Berkeley
Publications - 4
Citations - 326
A. Casotto is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: Iterative design & Simulated annealing. The author has an hindex of 4, co-authored 4 publications receiving 323 citations.
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Journal ArticleDOI
A Parallel Simulated Annealing Algorithm for the Placement of Macro-Cells
TL;DR: A modification of the classical Simulated Annealing algorithm for the macro-cell placement problem is proposed for implementation on multiprocessor systems and experimental results show that the new algorithm obtains results comparable in quality to those of the single processor version.
Proceedings ArticleDOI
A Constraint-driven Placement Methodology For Analog Integrated Circuits
TL;DR: A new constraint-driven methodology for the placeinent of analog IC's is described, where electrical performance specifications are automatically translated into constraints on the layout parasitics and these constraints and the seiisiitivity iiiforinatioii of the circuit are used to control a Simulated Annealingbased placement algorithm.
Proceedings ArticleDOI
Design management based on design traces
TL;DR: VOV is an automatic manager for VLSI design that offers a wide variety of services related to design management, such as coordination of team design, automatic execution of CAD transactions, capture of design history and data dependencies.
Journal ArticleDOI
Automated design management using traces
TL;DR: An automatic management system for CAD based on the idea that CAD tools can leave a trace of their execution is proposed, which is both a record of the design activity and a graph representing the dependencies among the design objects.