U
U. Choudhury
Researcher at University of California, Berkeley
Publications - 10
Citations - 599
U. Choudhury is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: Physical design & Routing (electronic design automation). The author has an hindex of 9, co-authored 10 publications receiving 583 citations.
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A Top-Down, Constraint-Driven Design Methodology for Analog Integrated Circuits
Henry Chang,A. Sangiovanlli-Vincentelli,F. Balarin,Edoardo Charbon,U. Choudhury,G. Jusuf,E. Liu,E. Malavasi,R. Neff,Paul R. Gray +9 more
TL;DR: A top-down, constraint-driven design methodology for analog integrated circuits and some of the tools that support this methodology are described, including behavioral simulation tools, tools for physical assembly, and module generators.
Journal ArticleDOI
Automatic generation of analytical models for interconnect capacitances
TL;DR: An analytical-model generator for interconnect capacitances is presented, which obtains analytical expressions of self and coupling capacitance of interconnects for commonly encountered configurations, based on a series of numerical simulations and a partial knowledge of the flux components associated with the configurations.
Proceedings ArticleDOI
Constraint generation for routing analog circuits
TL;DR: It is hoped that the constraint-based approach suggested in this paper, if applied to both placement and routing, will reduce the need of time consuming layout-extraction-simulation iterations in the physical design phase of analog circuits.
Journal ArticleDOI
Constraint-based channel routing for analog and mixed analog/digital circuits
TL;DR: It is observed that perfect matching is not possible for a matched pair of nets with intersecting horizontal spans, so a technique to achieve almost perfect mirror symmetry is presented for such pairs of nets.
Proceedings ArticleDOI
A Constraint-driven Placement Methodology For Analog Integrated Circuits
TL;DR: A new constraint-driven methodology for the placeinent of analog IC's is described, where electrical performance specifications are automatically translated into constraints on the layout parasitics and these constraints and the seiisiitivity iiiforinatioii of the circuit are used to control a Simulated Annealingbased placement algorithm.