A. Castillo Atoche

TL;DR: The innovative algorithmic idea is to incorporate into the DEDR-optimized fixed-point iterative reconstruction/enhancement procedure the convex convergence enforcement regularization via constructing the proper multilevel projections onto convex sets (POCS) in the solution domain.

TL;DR: A design methodology for computing the time-varying coefficients of the fading channel simulators using consumer-designed graphic processing units (GPUs) is proposed and it is possible for nonspecialized users in parallel computing to accelerate their simulation developments when compared to conventional software.

TL;DR: This paper proposes a series of related laboratory projects to the image processing area through reconfigurable integrated circuits like FPGA (field programmable gate array), and the algorithms proposed in these laboratory projects are coded in C++ and implemented in the embedded microcontroller Microblaze.

TL;DR: A new reconfigurable architecture for the generation of GRN at each clock cycle is proposed, consisting in the polynomial approximation of the inverse method, implemented through parallel computing techniques using processor arrays.

TL;DR: A new approach for near-real-time enhancement of large-scale Geospatial and aerial remote sensing imagery that aggregates descriptive and Bayesian convex regularization paradigms for solving the image reconstruction inverse problems with efficient systolic-based neural network (NN) computing is addressed.