The following topics are dealt with: dynamic translation; profile-based optimizations; EPIC compilation; code scheduling; code optimization; dynamic adaptive compilation; and performance monitoring.

International Symposium on Code Generation and Optimization (CGO)

The discrete Hartley transform (DHT) has proved to be a valuable tool in digital signal/image processing and communications and has also attracted research interests in many multidimensional applications. Although many fast algorithms have been developed for the calculation of one- and two-dimensional (1-D and 2-D) DHT, the development of multidimensional algorithms in three and more dimensions is still unexplored and has not been given similar attention; hence, the multidimensional Hartley transform is usually calculated through the row-column approach. However, proper multidimensional algorithms can be more efficient than the row-column method and need to be developed. Therefore, it is the aim of this paper to introduce the concept and derivation of the three-dimensional (3-D) radix-2 /spl times/ 2 /spl times/ 2 algorithm for fast calculation of the 3-D discrete Hartley transform. The proposed algorithm is based on the principles of the divide-and-conquer approach applied directly in 3-D. It has a simple butterfly structure and has been found to offer significant savings in arithmetic operations compared with the row-column approach based on similar algorithms.

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Radix-2 /spl times/ 2 /spl times/ 2 algorithm for the 3-D discrete Hartley transform

We propose a hierarchical simulation methodology to assist application development on System-on-Chip architectures. Hierarchical simulation involves simulation of a SoC based system at different levels of abstraction. Thus, it enables a system designer to exploit simulation speed vs. accuracy of results trade-offs. Vertical simulation is a special case of hierarchical simulation, where a feedback mechanism between the different simulation levels helps in "interpreting" the results of stand-alone simulations in the system-wide context. The paper presents an approach to perform vertical simulation of a class of applications under a simplified scenario.

A hierarchical simulation framework for application development on system-on-chip architectures

Many of the modulation methods currently in use suffer from a high Peak-to-Average power Ratio (PAR), also known as the Crest Factor (CF). The Global System for Mobile communication (GSM) is a widespread second-generation (2G) system that uses constant envelope Gaussian minimum shift keying modulation. The advantage achieved by constant envelope modulation is the possibility of using power-efficient power amplifiers (PAs). However, it might be beneficial to combine the carriers in a digital intermediate frequency in order to reduce the number of analogue components. The drawback with this is that the signal is no more a constant envelope signal, but it has a strongly fluctuating envelope with a high CF. Enhanced Data rates for GSM Evolution (EDGE) is an enhancement to the GSM system with the primary objective of tripling the on-air data rate while meeting essentially the same bandwidth occupancy of the original GSM signal. Also in the case of EDGE, if the carriers are combined prior to amplification we would end up with the same high CF problem. Wideband Code Division Multiple Access (WCDMA) has been selected by the European Telecommunications Standards Institute for wideband wireless access to support third-generation (3G) services. Orthogonal Frequency Division Multiplexing (OFDM) is commonly considered to be a technical solution for fourth-generation (4G) services. In both cases, the transmitted signal is generated by adding together a large number of statistically independent signals, which leads to a signal with a high CF. The high CF sets strict requirements for the linearity of the PA. In order to limit the adjacent channel leakage, it is desirable for the PA to operate in its linear region. High linearity requirements for the PA leads to low power efficiency and therefore to high power consumption. An alternative to the expense of a wide-dynamic-range PA is the use of deliberate clipping to digitally distort the signal so that the signal quality is still maintained at a sufficient level. As an extra advantage, the decreased CF gives rise to the possibility of utilizing the dynamic range of the digital circuitry and digital-to-analog converter efficiently. This thesis discusses digital modulator design, concentrating on CF reduction algorithms. Two modulators, one capable of generating GSM, EDGE and WCDMA sig-

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Digital modulators with crest factor reduction techniques

In this paper, we present an analysis of low complexity signal processing algorithms capable of identifying special noises, such as the sounds of forest machinery (used for forestry, logging). Our objective is to find methods that are able to detect internal combustion engines in rural environment, and are also easy to implement on low power devices of WSNs (wireless sensor networks). In this context, we review different methods for detecting illegal logging, with an emphasis on autocorrelation and TESPAR audio techniques. The processing of extracted audio features is to be solved with limited memory and processor resources typical for low cost sensors modes. The representation of noise models is also considered with different archetypes. Implementations of the proposed methods were tested not by simulations but on sensor nodes equipped with an omnidirectional microphone and a low power microcontroller. Our results show that high recognition rate can be achieved using time domain algorithms and highly energy efficient and inexpensive architectures.

Time Domain Audio Features for Chainsaw Noise Detection Using WSNs

A large number of fast Fourier transform (FFT) algorithms have been developed over the years. Among these, the most promising are the radix-2, radix-4, split-radix, fast Hartley transform (FHT), quick Fourier transform (QFT), and the decimation-in-time-frequency (DITF) algorithms. We present a rigorous analysis of these algorithms that includes the number of mathematical operations, computational time, memory requirements, and object code size. The results of this work will serve as a framework for creating an object-oriented, poly-functional FFT implementation which will automatically choose the most efficient algorithm given user-specified constraints.

https://ieeexplore.ieee.org/iel3/4754/13182/00598704.pdf

A. Choudary

Papers

Benchmarking of FFT algorithms