Recent reference clock distribution technologies are reviewed. Performance concepts and specification methodologies for synchronization system designs are then summarized. The focus is on the common master-slave synchronization designs, generally consisting of three subsystems: the primary clock supply, the slave clock supply, and the clock distribution system overlaid on the digital network. Network synchronization performance is specified with relative clock frequency stability and accuracy of the corresponding reference clock. An overview is also given of clock and jitter and wander specification methodologies discussed in CCITT. >

Performance aspects of reference clock distribution for evolving digital networks

The present invention relates to methods for reducing transients in a redundant clock system forming part of a switch in a telecommunication network. In general, the transients, normally in the form of phase steps, are caused by reconfigurations in the clock system. Examples of reconfigurations are an inclusion or an exclusion of a redundant clock generating circuit, referred to as a plane, or an activation of a network synchronization. In accordance with a general inventive concept, these transients are eliminated by successively adding an increment to a variable representative of a physical quantity in the clock generating system. In the case of an inclusion of a plane or an activation of the network synchronization, a positive increment is successively added to the gain of an amplifier. In the case of an exclusion of a plane, an increment is successively added to a phase difference representing signal.

A method for reducing transients in a clock signal generating system

System considerations and precise clock distribution technology are discussed for high-speed fiber-optic systems such as broadband ISDN (integrated services digital network). A precise oscillator is in the central office provides a frequency standard. In each local office, a precise phase-locked loop recovers the standard clock signal. Methods are proposed for fast phase-locking and reducing the slip that occurs when the standard clock signal input is absent. >

http://ieeexplore.ieee.org/iel2/717/971/00025980.pdf

A. Hamanaka

Papers

Precise clock distribution for synchronous broadband transmission network