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A.J.C. van Gemund
Researcher at Delft University of Technology
Publications - 41
Citations - 1958
A.J.C. van Gemund is an academic researcher from Delft University of Technology. The author has contributed to research in topics: Fault (power engineering) & Performance prediction. The author has an hindex of 15, co-authored 41 publications receiving 1761 citations. Previous affiliations of A.J.C. van Gemund include NXP Semiconductors.
Papers
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Proceedings Article
Automatic Parallel Program Generation and Optimization from Data Decompositions
TL;DR: It is shown that by rewriting calculus expressions, Single Program Multiple Data (SPMD) code can be generated for shared-memory as well as distributed-memory parallel processors.
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FLB: Fast Load Balancing for distributed-memory machines
TL;DR: It is proven that FLB is essentially equivalent to the existing ETF scheduling algorithm of O(W(E+V)P) time complexity and consistently outperforms multi-step algorithms such as DSC-LLB that also have higher cost.
Proceedings ArticleDOI
A model-based approach to sequential fault diagnosis
TL;DR: A model-based approach to derive tests and test sequences for sequential fault diagnosis that offers advantages over methods that are based on test coverage of explicit fault states, represented in matrix form is presented.
Proceedings ArticleDOI
LLB: A fast and effective scheduling algorithm for distributed-memory systems
TL;DR: In this article, a list-based load balancing (LLB) algorithm is proposed for compile-time task scheduling on distributed-memory machines, which is intended as a cluster-mapping and task ordering step in the multi-step class of scheduling algorithms.
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A probabilistic approach to parallel system performance modelling
TL;DR: This paper describes several extensions and improvements to a previously introduced methodology, based on an extension of queueing networks, that extend the set of machine model building blocks, a new algorithm for the prediction of multiple-class parallel section completion times, and it is shown how programs containing conditional statements at the program level and memory hierarchies at the machine level are modelled.