In this paper we propose a robust technique to minimize multiple input digital circuits. This technique is simple and efficient to determine the minimum number of gates required to realize a multiple input digital circuit. Rather than using sizeable truth table for multiple input combinational circuits having at least one operation per minterms, proposed technique produced a minimal solution by breaking the minterms and arranging them in adjacent groups. This technique also overcomes the problems related to simplification using Karnaugh Map for more than four inputs system. Also we have proposed an algorithm to implement this technique in Java programming language and out provide results.

https://ijoaemorg.files.wordpress.com/2017/07/020600342.pdf

Software Implementation of Break-Up Algorithm for Logic Minimization

A method for finding out the simplest two-stage expression for a given multiple-output switching function requiring minimum number of AND-blocks is presented in this paper. The different component ...

A. K. Choudhuky

Papers

On a Method of Simplification of Multiple-output Switching Functions†