This review of design principles for implementation of a spiral inductor in a silicon integrated circuit fabrication process summarizes prior art in this field. In addition, a fast and physics-based inductor model is exploited to put the results contributed by many different groups in various technologies and achieved over the past eight years into perspective. Inductors are compared not only by their maximum quality factors (Q/sub max/), but also by taking the frequency at Q/sub max/, the inductance value (L), the self-resonance frequency (f/sub SR/), and the coil area into account. It is further explained that the spiral coil structure on a lossy silicon substrate can operate in three different modes, depending at first order on the silicon doping concentration. Ranging from high to low substrate resistivity, inductor-mode, resonator-mode, and eddy-current regimes are defined by characteristic changes of Q/sub max/, L, and f/sub SR/. The advantages and disadvantages of patterned or blanket resistive ground shields between the inductor coil and substrate and the effect of a substrate contact on the inductor are also addressed in this paper. Exploring optimum inductor designs under various constraints leverages the speed of the model. Finally, in view of the continuously increasing operating frequencies in advancing to new generations of RF systems, the range of feasible inductance values for given quality factors are predicted on the basis of optimum technological features.

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On the design of RF spiral inductors on silicon

Silicon technology has progressed over the last several years from a digitally oriented technology to one well suited for microwave and RF applications at a high level of integration. Technology scaling, both at the transistor and back-end metallization level, has driven this progress. CMOS technology is ideally suited for low-noise amplification and receiver applications, but the fundamental breakdown voltage is lower than that of equivalent Si/SiGe HBTs. High-quality passive devices are equally important, and improvements in metallization technology are resulting in higher quality inductors. This paper summarizes the silicon technology issues associated with RF "system-on-a-chip" applications.

Silicon technology tradeoffs for radio-frequency/mixed-signal "systems-on-a-chip"

Wafer-transfer technology (WTT) has been applied to transfer RF inductors from a silicon wafer to an opaque plastic substrate (FR-4). By completely eliminating silicon substrate, the high performance of integrated inductors (Q-factor > 30 for inductance /spl sim/3 nH with resonant frequency /spl sim/23 GHz) has been achieved. Based on the analysis of a modified /spl pi/-network model, our results suggest that the performance limitation is switched from being a synthetic mechanism of substrate and metal-ohmic losses on low resistivity Si-substrate to merely a metal-ohmic loss on FR-4. Thus, the inductor patterns, which are optimized currently for RFICs on silicon wafer, can be further optimized to take full advantage of the WTT on new substrate from the newly obtained design freedom.

High-performance inductors on plastic substrate

This letter describes a metal/polysilicon damascene gate technology for RF power LDMOSFETs. We compare the performance of SOI LDMOSFETs with metal/polysilicon damascene gates to that of identical devices with n/sup +/ polysilicon gates. The gate sheet resistance of the metal/polysilicon gate was 0.2 /spl Omega//sq. This very low sheet resistance greatly improved f/sub max/ and peak PAE, especially for the wide gate fingers that are critical in RF power applications. With a 140 /spl mu/m gate finger width, f/sub max/ was improved from 5 GHz to 25 GHz, and peak PAE at 1.9 GHz was improved from 12% to 52%.

A metal/polysilicon damascene gate technology for RF power LDMOSFETs

The present disclosure relates to semiconductor structures and, more particularly, to radio frequency (RF) switches with airgap structures and methods of manufacture. The structure includes a substrate with at least one airgap structure formed in a well region under at least one gate structure, and which extends to a junction formed by a source/drain region of the at least one gate structure.

Radio frequency switches with air gap structures

High performance digital-analog mixed devices are fabricated on a high resistivity MCZ Si substrate with low oxygen in order to suppress substrate noise from digital to analog circuits The low oxygen prevents substrate resistivity reduction due to thermal donor occurring during device fabrication process Good characteristics of digital, analog and power amplifiers can be realized by optimizing the process of oxynitride, halo implantation and salicide In 011 /spl mu/m CMOS, high drivability, that is, 770 /spl mu/A//spl mu/m for NMOS and 330 /spl mu/A//spl mu/m for PMOS was achieved at Ioff=10/sup -9/ A//spl mu/m And fT value of 90 GHz for NMOS and 48 GHz for PMOS can be achieved Additionally, high efficiency of 68% at 2 GHz operation can be realized in power amplifier with 030 /spl mu/m gate length

A. Kawasaki

Papers

High performance digital-analog mixed device on an Si substrate with resistivity beyond 1 k/spl Omega/ cm