The present invention is directed to delta modulation in which the modulation level is optimized to improve overall system performance. A delta modulator in accordance with the invention includes a step size controller having a overload detector, a step size generator and a modulation level regulator. The overload detector monitors the output serial bit stream and produces a signal indicative of whether overload conditions are present. The step size generator produces steps of varying sizes in response to an input signal. The modulation level regulator monitors the signal output from the overload detector and outputs a modulated signal when the overload detector output has reached at least a certain threshold level. The modulation level regulator output is received at the step size generator input.

Delta modulator with pseudo constant modulation level

To apply multiple-valued logic (MVL) to digital filter design, a novel structure of digital filter, named signed binary delta modulation digital filter (SBDM-DF), is presented. The SBDM-DF uses a tristate quantizer allowing (1, 0, -1) states to encode the input signal. Signed binary number representation is used for filter coefficients in order to attain carrier-free addition with signed binary adder tree (SBAT). In hardware realization, ternary logic circuits can be adopted to increase the carried information per wire. From the analysis of SNR (signal-to-noise-ratio) characteristics of SBDM and conventional delta modulation (DM), it is found that the sampling frequency of SBDM can be reduced by at least one-half, relative to DM, for the same signal quality. The design procedure of SBDM-DF is illustrated by a typical low-pass filter using the Kaiser-windowing technique. >

Signed binary delta modulation digital filter

The commenters note that there is a large body of literature treating architectures similar to that in the above-titled paper by H. Qiuting and G.S. Moschytz (ibid., vol. 39), no. 9, pp. 658-663, Sept. 1992), and they provide a list of references thereto. >

Comments on "analog FIR filters with an oversampled Sigma - Delta modulator

Ternary coding and triangular modulation

Implementation of Binary and Ternary Convolutional Codes on an FPGA

This correspondence shows a method for determining the ternary delta sequence of the third of the sum of two analog signals through their corresponding delta sequences. The hardware implementation proposed here is modular employing a universal logic T-gate which allows building both sequential and combinatorial circuits. The primary advantage of a ternary nonredundant symmetric presentation of the TDM over a binary DM presentation is the reduction of problems of carry propagation in arithemetic operation and reduction in connections and interconnections between chips and interchips.

A. Mavretic

Papers

Arithmetic ternary operations on delta-modulated signals and their application in the realization of digital filters