This paper presents a new formulation of digital filters that combines the description of signal-processing and arithmetic operations. This is done by noting that multiplication is a form of convolution and therefore normal one-dimensional scalar convolution is in fact two-dimensional binary convolution. This is generalized to multidimensions and can be applied with table-look-up and transform techniques. The result is a unified description that describes a digital filter structure down to the bit level.

Digital filter structures described by distributed arithmetic

A variable-passband, variable-phase digital filter in which Q digital samples of a signal are entered through (Q-1) delay lines, to be delayed into q two-bit adjacent doublets. Weighting tables in read only memories are addressed by each doublet. Each weighting table includes the results of linear combinations of the weights of doublets composed of bits of the same order multiplied by multiplier coefficients which are smaller than unity. Each integral portion of a result found in a table is applied at the same time as the fractional portions of the other results provided by the other tables to the addressing inputs of a programmed memory containing binary words. Binary words are addressed in the prorammed memory by the integral and fractional portions of the results found in the weighting tables. Each binary word has a value equal to the linear combination of the corresponding values of the samples of the signal by the multiplier coefficients.

Variable-passband variable-phase digital filter

This paper gives a detailed description of coefficient quantization errors of the distributed arithmetic, which means a recently introduced technique for the realization of the inner product of two vectors where conventional multipliers and adders are replaced by a memory and an accumulator. For systems excited by uniformly distributed white noise, an expression for the total power of the output error is derived. It may be compared with an earlier error analysis which, as will be shown, is too pessimistic for small vector lengths. In that case the total round-off error is partly correlated with the input signals while for large vector lengths usual errors due to the quantization of individual coefficients vanish and thus the total error can be described by an independent noise source at the output.

http://ieeexplore.ieee.org/iel5/31/23464/01084294.pdf

Quantization error analysis of the distributed arithmetic

A digital and a multiplication method are described, which lead to an efficient architecture for hardware implementation of digital FIR and IIR filters into FPGAs. The multiplications of input sample data and delayed sample data with filter coefficients are performed by addressing look-up tables in which corresponding multiplication results are prestored. The size of the look-up tables is reduced by storing only those multiplication results which cannot be obtained by a shifting operation performed on the other pre-stored multiplication results, the input sample data, or the delayed sample data. Thereby, the size of the look-up tables can be compressed significantly such that an implementation of large digital filters into FPGAs is possible.

Digital filter and method for performing a multiplication based on a look-up table

A recently proposed method to implement digital filters using ROM can also be employed to implement multiplication by a constant. This note discusses alternate implementations for digital filter sections substituting memory for logic and points out the possible advantage of doing so.

A. Peled

Papers

A note on implementation of digital filters