This paper is a review of methods and techniques used for precise measurement of time intervals (TIs) or precise conversion of TIs to digital data. The following methods are described: the counter method and averaging, time stretching, time-to-amplitude conversion followed by analogue-to-digital conversion, the Vernier method, conversion utilizing tapped delay lines, and interpolation methods. Special attention has been paid to converters utilizing integrated delay lines for digital conversion of TIs, including designs with phase-locked loop and delay-locked loop circuits. This review is illustrated by design examples and contains a comprehensive list of references.

https://iopscience.iop.org/article/10.1088/0026-1394/41/1/004/pdf

Review of methods for time interval measurements with picosecond resolution

A high-resolution time-to-digital converter (TDC) implemented in a general purpose field-programmable-gate-array (FPGA) is presented. Dedicated carry lines of an FPGA are used as delay cells to perform time interpolation within the system clock period and to realize the fine time measurement. Two Gray-code counters, working on in-phase and out-of-phase system clocks respectively, are designed to get the stable value of the coarse time measurement. The fine time code and the coarse time counter value, along with the channel identifier, are then written into a first-in first-out (FIFO) buffer. Tests have been done to verify the performance of the TDC. The resolution after calibration can reach 50 ps

A high-resolution time-to-digital converter implemented in field-programmable-gate-arrays

A deep sub-nanosecond resolved CMOS pulse-shrinking delay element used in the time-to-digital converter (TDC) is proposed. The pulse shrinking capability of the element is controlled by the dimension ratio of the adjacent gates. This control mechanism is completely different from the bias adjustment adopted in the conventional pulse-shrinking element. Without the need of continuous calibration, the presented element possesses not only extremely fine resolution, small single-shot errors, low power consumption, but also good insensitivity to the supply voltage variation. Being fabricated with 0.35 /spl mu/m CMOS technologies, the TDC made of the new elements has been measured to have a resolution of 68 ps. The effective resolution only varies 1.5 ps for a rather large supply voltage range from 3.5 to 4.5 V. The size of the circuit is 0.35 mm/spl times/0.09 mm only, excluding the I/O pads. Under a single 3.3-V power supply, the static power dissipation, including the I/O pads, is 1 /spl mu/W. The average power consumption is measured to be merely 1.2 mW under a measurement rate of 100 ksps.

A CMOS pulse-shrinking delay element for time interval measurement

A new design of a time-to-digital converter (TDC) implemented on an FPGA chip with amorphous antifuse structures is presented. Time coding with 200-ps resolution (LSB), 10-ns range, and very short conversion time is realized by two tapped delay lines working in-a differential mode. Thanks to the local feedback loops, the output from the delay line is obtained directly in "1-out-of-N" code and then converted to 6-bit natural binary. Within the temperature range from 0/spl deg/C to 45/spl deg/C, the time offset at the output is constant, the resolution changes by /spl plusmn/0.02 LSB, and the offset-corrected integral linearity error is less than 1 LSB.

Field-programmable-gate-array-based time-to-digital converter with 200-ps resolution

This paper describes the logic and performance of an interpolating time counter integrated on a single FPGA device. The resolution of 100 ps (LSB) was obtained because of the new design of the FPGA delay lines used for precise time-to-digital conversion, and the use of enhanced CMOS FPGA technology. The worst-case random error of 170 ps has been lowered to 70 ps by software correction of the nonlinearity of the delay lines. The counter can measure time intervals from 0-43 s and frequency up to 200 MHz. The maximum power consumption of the counter chip is 260 mW.

Interpolating time counter with 100 ps resolution on a single FPGA device

In this paper, we present a design and test results of the interpolating time counter implemented on a single field programmable gate array (FPGA) chip. The counter contains two 6-bit time-to-digital converters (TDCs), each having 200-ps resolution (LSB) within 10 ns range, and the 32-bit, 100-MHz real-time counter, which is also used for frequency measurement. The utilization of the logic cells on the FPGA chip is 93%. The software correction of the TDC's nonlinearity errors resulted in lowering the random error of the counter to 0.65 LSB or 129 ps (RMS).

A. Poniecki

Papers

Field-programmable-gate-array-based time-to-digital converter with 200-ps resolution

Single-chip interpolating time counter with 200-ps resolution and 43-s range

Optimized data processing in precision laser rangefinder with embedded microcontroller