Comprehensive Survey of Image Steganography: Techniques, Evaluations, and Trends in Future Research

With the digitalization of information, a lot of multimedia data are under attack, information security has become a key issue of public concern. Image steganography, aiming at using cover images to convey secret information has become one of the most challenge and important subjects in the field of information security recently. Different from the traditional image steganography, coverless image steganography does not need to employ the designated cover image for embedding the secret data but directly transfers secret information through its own properties such as pixel brightness value, color, texture, edge, contour and high-level semantics. Therefore, it radically resist the detection of steganalysis tools and significantly improves the security of the image. Its basic idea is to analyze the attributes of the image and map them to the secret information according to certain rules based on the characteristics of the attributes. This paper includes more than 50 key contributions to provide a comprehensive survey in this field, covers the main aspects of coverless image steganography research: the fundamental frameworks, pre-processing, feature extraction, generation of hash sequence and mapping relationships. The existing methods are evaluated and the prospect of future work is also summarized.

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Coverless Image Steganography: A Survey

With the growth of information technology, information security is a major concern in the interactive environment, where there is no security for the messages send to and from the receiver. A technology named image steganography has been employed that ensures security to the covert communication and safeguarding the information. Image steganography hides the secret message in any of the recipient images and sends the secret message such that the message is visible only to the sender and the receiver. This paper proposes a method for image steganography using sparse representation, and an algorithm named Particle Swarm Optimization (PSO) algorithm for effective selection of the pixels for the purpose of embedding the secret audio signal in the image. PSO-based pixel selection procedure uses a fitness function that depends on the cost function. Cost function calculates the edge, entropy, and intensity of the pixel for evaluating fitness. Simulation has been done and comparison of the PSO with the other existing methods in terms of Peak-Signal-to-Noise-Ratio (PSNR) and Mean Square Error (MSE) determines the proposed PSO, as an effective method. The proposed method achieved a better PSNR and MSE values of 47.6 dB and 0.75 respectively.

A sparse representation based image steganography using Particle Swarm Optimization and wavelet transform

Image steganography using exploiting modification direction for compressed encrypted data

Steganography is a data-concealing technique that provides a covert communication. This paper proposes a spatial domain color steganography method that uses a neighboring pixel-pair differencing co...

An adaptive color image steganography method using adjacent pixel value differencing and LSB substitution technique

The most crucial task in real-time processing of steganography algorithms is to reduce the computational delay and increase the throughput of a system. This critical issue is effectively addressed by implementing steganography methods in reconfigurable hardware. In the proposed framework, a new high-speed reconfigurable architectures have been designed for Least Significant Bit (LSB) or multi-bit based image steganography algorithm that suits Field Programmable Gate Arrays (FPGAs) or Application Specific Integrated Circuits (ASICs) implementation. The architectures are designed and instantiated to implement the complete steganography system. The proposed system is competent enough to provide larger throughput, since high degrees of pipelining and parallel operations are incorporated at the module level. The evolved architectures are realized in Xilinx Virtex-II Pro XC2V500FG256-6 FPGA device using Register Transfer Level (RTL) compliant Verilog coding and has the capacity to work in real-time at the rate of 183.48 frames/second. Prior to the FPGA/ASIC implementation, the proposed steganography system is simulated in software to validate the concepts intended to implement. The hardware implemented algorithm is tested by varying embedding bit size as well as the resolution of a cover image. As it is clear from the results presented that the projected framework is superior in speed, area and power consumption compared to other researcher's method.

Design and development of new reconfigurable architectures for LSB/multi-bit image steganography system

Exploiting modification direction (EMD)-based image steganography algorithm has higher embedding efficiency, low distortion, and best security that finds application in secure communication, data protection, access control in digital content distribution, etc., EMD steganography encapsulates secret digit represented in (2n + 1)-ary notational system by increasing or decreasing one of the n cover pixels by one. New high-speed reconfigurable architectures and field programmable gate array (FPGA) implementation of EMD based image steganography algorithms have been proposed. Although, earlier work on FPGA implementation of steganography algorithms offer higher speed, low chip area, and better throughput it usually operates on a fixed number of pixels. The proposed system works well for both arbitrary numbers of pixel groups and variable image resolution. The developed system is capable of embedding a secret message from two to eight-pixel groups with an image resolution of 512 × 512 pixels at a real-time video rate of 549 frames/s.. The complete design is implemented using RTL compliant Verilog code which fits into a single FPGA/ASIC chip with a gate density of two million gates.

Novel high-speed reconfigurable FPGA architectures for EMD-based image steganography

Steganography is one in all the foremost persuasive approaches to mask the presence of hidden data inside a cover object. Images are one of the suitable cover objects for the Steganography. Current trends support, digital image files as the cover file to hide multiple secret images. Steganography presents the clandestine information can be covered in mediums like image, video and audio. This paper provides a LSB image Steganography technique to hide multiple secret images in a cover image which is in a YCbCr color space format using Integer Wavelet Transform (IWT). There is no optical variation between the stego image and the original cover image. The proposed hardware architecture gives very fast, programmable & cost effective hardware solution in the area of Secure Communication.

Image Steganography Using Integer Wavelet Transform Based on Color Space Approach

The most crucial task in real-time processing of image or video steganography algorithms is to reduce the computational delay and increase the throughput of a steganography embedding and extraction system. This problem is effectively addressed by implementing steganography hiding and extraction methods in reconfigurable hardware. This chapter presents a new high-speed reconfigurable architectures that have been designed for Least Significant Bit (LSB) and multi-bit based image steganography algorithm that suits Field Programmable Gate Arrays (FPGAs) or Application Specific Integrated Circuits (ASIC) implementation. Typical architectures of LSB steganography comprises secret message length finder, message hider, extractor, etc. The architectures may be realized either by using traditional hardware description languages (HDL) such as VHDL or Verilog. The designed architectures are synthesizable in FPGAs since the modules are RTL compliant. Before the FPGA/ASIC implementation, it is convenient to validate the steganography system in software to verify the concepts intended to implement.

A. R. Aswath

Papers

Design and development of new reconfigurable architectures for LSB/multi-bit image steganography system

Novel high-speed reconfigurable FPGA architectures for EMD-based image steganography

Image Steganography Using Integer Wavelet Transform Based on Color Space Approach

Design of Reconfigurable Architectures for Steganography System