Fast Fourier Transform

Frequency analysis using DFT (discrete Fourier transform) or its faster computational technique (FFT) is an obvious choice for the entire image and signal processing domain where spectral leakage or picket fence effect is a major problem. Earlier works describe the software and ROM-based implementation of windowing functions to overcome the above-mentioned problems during spectral analysis. In this work we have proposed a CORDIC (co-ordinate rotation digital computer)-based unified windowing architecture to remove the spectral leakage, picket fence effect and resolution problems with different tradeoff between mainlobe and sidelobe in the frequency domain. A parallel-pipelined architecture has been adopted for the present design to ensure high throughput for real-time applications with the latency equal to twice of CORDIC length plus three extra cycles. This unified architecture includes a combination of linear CORDIC and circular CORDIC with FIFO and a few multiplexers where the selection of window and its length are user defined. We have synthesised this architecture with 0.18 μm CMOS technology using Synopsys Design Analyser. The total estimated dynamic power was found to be 350 mW with an operating frequency of 125 MHz and total cell area 11 mm2 (approximately).

CORDIC-based unified VLSI architecture for implementing window functions for real time spectral analysis

https://cyberleninka.org/article/n/701322.pdf

Power system low frequency oscillation mode estimation using wide area measurement systems

CORDIC-based VLSI architecture for real time implementation of flat top window

The prevalent need for very high speed digital signals processing in wireless communications has driven communications system to higher levels of performance. The objective of this paper is to propose a novel structure for efficient implementation of the Fast Fourier Transform (FFT) processor to meet the requirements of high speed wireless communication system standards. Based on the algorithm, architecture analysis, a design of pipeline Radix 22 SDF FFT processor based on the digit-slicing Multiplier-Less technique is proposed. Furthermore, this paper proposes an optimal constant multiplication arithmetic design to multiply a fixed point input by means of one of the several present twiddle factor constants. The proposed architecture was simulated using MATLAB software and the Field Programmable Gate Array (FPGA) Virtex 4 was targeted to synthesise the proposed architecture. The design was tested in real hardware of TLA5201 logic analyzer and the ISE synthesis report resulted in high speeds of 669.277 MHz with a total equivalent gate count of 14,854. This is a significant improvement over the Radix 22 DIF SDF FFT processor from which it can be concluded that the proposed pipeline Radix 22 DIF SDF FFT processor based on digit-slicing multiplier-less is capable of solving the problems that affect the capabilities of most high speed wireless communication systems in FFT and possesses huge potential for future research.

A. Ragoub

Papers

Implementation of a high speed Fast Fourier Transform VLSI chip