The relation between yield and early failures as encountered in the field was investigated with several high volume IC's manufactured in several processes. A clear correlation between yield and reliability was found that obeys a simple model. The model also provides the ability to predict the FIT or PPM level of a given IC based on its yield. Using these results we illustrate how a wafer fab may improve the reliability level of its products in a controlled way.

Relation between yield and reliability of integrated circuits: experimental results and application to continuous early failure rate reduction programs

A system and method for determining the early life reliability of an electronic component, including classifying the electronic component based on an initial determination of a number of fatal defects, and estimating a probability of latent defects present in the electronic component based on that classification with the aim of optimizing test costs and product quality.

System and method for estimating reliability of components for testing and quality optimization

Relation between yield and reliability of integrated circuits and application to failure rate assessment and reduction in the one digit FIT and PPM reliability era

Studies suggest the use of "dropped in" test chips as an instrument for monitoring the quality of each manufacturing step of VLSI chips, and as a cost-effective procedure for eliminating potentially "bad" wafers. Here, the yield and long-term reliability are estimated on the basis of the test chips manufactured on the same wafer as the fully functional chips. Only wafers accepted based on this preliminary characterization are subjected to a complete MIL-38510 (or equivalent) characterization of all packaged chips. Successful application of this principle, however, depends on several things, such as degree of similarity between the structures on the test chip versus the structures on the fully functional chips, on the number of test chips, their location within the wafer and so on. In particular, it has been found necessary to take into account that the distribution of defects is not purely random, for example there may be a tendency that the defect density varies between the center and the edge of the wafer, and adjacent chips are often found to be statistically dependent. The study presented in this paper seeks to determine the effectiveness of estimating the wafer quality, in particular in terms of wafer yield. A Monte Carlo simulation model has been developed, that allows us to compare yield estimates with "actual" wafer yields, under various scenarios of defect density variation, test structure scaling factor, and test chip sample size and location within the wafer.

Effectiveness of yield-estimation and reliability-prediction based on wafer test-chip measurements

L'invention concerne un systeme et un procede permettant de determiner la fiabilite precoce d'un composant electronique. Ce systeme et ce procede consistent a classifier ledit composant electronique en fonction d'une definition de depart de plusieurs defauts fatals, et a estimer la probabilite de defauts latents presents dans ce composant electronique en fonction de cette classification, de sorte a optimiser les couts des tests et la qualite du produit.

Syteme et procede permettant d'evaluer la fiabilite de composants pour optimiser les tests et la qualite

A methodology for wafer level reliability prediction is described. Accelerated lifetests performed on specifically designed test structures allowed us to correlate reliability with elementary process yields. These elementary yields were extracted for each test structure (which characterizes a process step) from data obtained after wafer level tests. The wafer "peripheral" area, on which was detected a significant number of clustered defects at wafer level, presented few failures during the accelerated lifetest, showing that the geographical origin of the devices does not significantly affect the reliability.

http://ieeexplore.ieee.org/iel3/3902/11331/00513976.pdf

A. Touboul

Papers

Evidence of a correlation between process yields and reliability data for a rad-hard SOI technology