This paper presents the design of an n-type bulk-driven MOSFET which is intended to facilitate the scaling of analogue circuitry down to 0.7 V, the minimum supply voltage predicted for the end of bulk CMOS. The bulk-driven MOSFET design will be carried out in two parts using the design rules of a standard 90 nm bulk CMOS technology. First, the impact of gate oxide scaling will be investigated to see how the bulk transconductance behaves as the oxide thickness is varied. Results will indicate that the oxide scaling requirements of a MOSFET can be relaxed by 0.4 nm when the bulk is used as the input terminal rather than the gate. Second, by taking advantage of a larger oxide thickness, it will be shown that a delta-doped profile is capable of improving the intrinsic gain and cut-off frequency of a bulk-driven MOSFET by as much as 429% and 71%, respectively, when compared to a uniformly doped bulk-driven device consistent with the specifications of a 90 nm bulk CMOS process. Overall, the delta-doped bulk-driven MOSFET will exhibit a long-channel bulk-to-gate transconductance ratio equal to 0.51, compared to 0.27 in the uniformly doped device (the gate transconductance was the same in both devices). The new delta-doped design will also increase the bulk-driven-to-gate-driven cut-off frequency ratio to 0.095–0.492 for channel lengths ranging from 80–800 nm, which is a 16–34% improvement over the uniformly doped case. When used in a differential amplifier circuit, the delta-doped bulk-driven MOSFET was found to have a dc voltage gain 185% higher than that of a similar amplifier utilizing uniformly doped devices.

http://iopscience.iop.org/article/10.1088/0268-1242/25/11/115011/pdf

Designing bulk-driven MOSFETs for ultra-low-voltage analogue applications

Scaling the bulk-driven MOSFET into deca-nanometer bulk CMOS processes

In this paper, a low voltage bandgap reference (LVBR) is proposed and analyzed. An nMOS arrangement folded operational transconductance amplifier (OTA) is developed for the LVBR. From the Hspice simulation results, the proposed LVBR can be operated with sub-1V supply. The LVBR circuit, occupied an area of 0.12 mm/sup 2/, is design and fabricated in a doubly-poly quadruple-metal 0.35-/spl mu/m CMOS process. The circuit functions properly with minimum supply voltage of 0.88 V and consumes a power dissipation of 25 /spl mu/W. The circuit also provides a temperature coefficient of 20 ppm/K over a temperature range from -20 to 100/spl deg/C.

A low voltage CMOS bandgap reference

A bandgap reference with curvature corrected compensation which utilizes the subtraction of currents generated from complementary NMOS and PMOS bandgaps using MOS transistors in subthreshold is presented. A transimpedance amplifier with accurate input current compensation is used to overcome the problems due to input common range limitations of operational amplifiers. The bandgap reference uses power supply of 0.8V, the accuracy is 19ppm/K for 386mV in the temperature range of 0 to 130C. The PSRR is 24dB for 1kHz and 23dB for 10kHz.

Bandgap reference with curvature corrected compensation using subthreshold MOSFETs

Approval: __________________________________________ Committee Chair __________________________________________ Program Director __________________________________________ Dean of the KGCOE

/pdf/scaling-the-bulk-driven-mosfet-into-decananometer-bulk-cmos-4r8eg8ftj6.pdf

Scaling the bulk-driven MOSFET into decananometer bulk CMOS technologies

A sub-1 volt bandgap voltage reference is presented. The bandgap design utilizes the body-driven technique, which allows the bandgap voltage reference to operate at low voltages without requiring low threshold voltage devices. The technique provides larger input common-mode range, which is important in low voltage bandgap voltage reference circuits. The design features PMOS diodes to provide the negative and positive temperature coefficients. The complete design was simulated and laid out in AMI 0.6 /spl mu/m CMOS process. A minimum supply voltage of 0.8 V and a maximum current of 1.1 /spl mu/A were achieved. The design provides a temperature coefficient of 33 ppm//spl deg/C over a temperature range from 0 to 100/spl deg/C and occupies an area of 0.05 mm/sup 2/.

A. Yamazaki

Papers

A sub-1 volt CMOS bandgap voltage reference based on body-driven technique