Showing papers by "Aarno Parssinen published in 1999"
15 Feb 1999
TL;DR: In this paper, a 2GHz direct conversion receiver for third-generation mobile communications using wideband code division multiple access achieves -114dBm sensitivity for 128-kb/s data at 4.096-Mcps spreading rate.
Abstract: A 2-GHz direct conversion receiver for third-generation mobile communications using wide-band code division multiple access achieves -114-dBm sensitivity for 128-kb/s data at 4.096-Mcps spreading rate. The receiver is distributed on four dies. The active RC channel selection filter can be programmed to three different bandwidths from 5 to 20-MHz radio-frequency (RF) spacing; and the gain control is merged with filtering. RF and baseband chips use a 25-GHz, 0.3-/spl mu/m BiCMOS technology while the two analog-to-digital converters are implemented with a 0.5-/spl mu/m CMOS. The double-sideband noise figure is 5.1 dB at the 94-dB maximum voltage gain, and the IIP3 and ITP2 are -9.5 and +38 dBm, respectively, The receiver draws 128 mA from a 2.7-V supply.
187 citations
Patent•
21 May 1999TL;DR: In this paper, the buffer switching means are arranged to respond to a buffering command (fs/N, A, B) by coupling said first sampler circuit and said second sampler component to said buffering component.
Abstract: Electrical circuit (300, 500, 800, 900) has an input (301, 501, 801, 802, 901, 902) and an output (311, 502, OUT, I-OUT, Q-OUT). The circuit samples an input signal coupled to the input having a certain input frequency and converts the input signal into a certain output frequency at the output, the output frequency being lower than the input frequency. It comprises a first sampler circuit (302, 510, 803, 910) coupled to the input, a second sampler circuit (303, 520, 804, 920) coupled to the input, a buffering component (309, 509, 809, 903, 904) coupled to the output and buffer switching means (305-307, 514, 515, 811-818, 914, 915, 924, 925, 934, 935, 944, 945, 954, 955, 964, 965, 974, 975, 984, 985). The buffer switching means are arranged to respond to a buffering command (fs/N, A, B) by coupling said first sampler circuit and said second sampler circuit to said buffering component.
58 citations
Proceedings Article•
01 Jan 1999TL;DR: An analog baseband circuitry for a WCDMA direct conversion receiver that includes a channel selection filtering and amplification with an adjustable gain in a merged manner and the active RC technique is applied.
Abstract: An analog baseband circuitry for a WCDMA direct conversion receiver is described. The circuitry includes a channel selection filtering and amplification with an adjustable gain in a merged manner. The active RC technique is applied. The filter bandwidth can be set to 2MHz, 4MHz or 8MHz and the gain can be controlled from -9dB to 69dB in 3dB steps. The filter frequency response is tuned with binary weighted switchable capacitor matrices. At the 2MHz bandwidth the chip consumes 39mA from a 2.7V supply. The chip has been fabricated with a 0.35µm BiCMOS process.
13 citations
13 Jun 1999
TL;DR: In this paper, a direct conversion RF front-end receiver chip, which can be used in the 3rd generation mobile communications, is introduced, consisting of a LNA, quadrature mixers and a 90/spl deg/LO phase shift network.
Abstract: A direct conversion RF front-end receiver chip, which can be used in the 3rd generation mobile communications, is introduced. The RF chip consists of a LNA, quadrature mixers and a 90/spl deg/ LO phase shift network. It uses a 25 GHz f/sub t/ BiCMOS process with a 0.35 /spl mu/m MOS gate length. The front-end has a 27.5 dB voltage gain, 4 dB NF (DSB), -9 dBm IIP3 and +43 dBm IIP2. It draws 41 mA from a 2.7 V supply.
11 citations