Proceedings of world academy of science, engineering and technology, vol 8

Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design. 

This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures.

KEY FEATURES
* A definitive guide to on-chip communication architectures, explaining key concepts, surveying research efforts and predicting future trends
* Detailed analysis of all popular standards for on-chip communication architectures
* Comprehensive survey of all research on communication architectures, covering a wide range of topics relevant to this area, spanning the past several years, and up to date with the most current research efforts
* Future trends that with have a significant impact on research and design of communication architectures over the next several years

On-Chip Communication Architectures: System on Chip Interconnect

Toward the tools selection in model based system engineering for embedded systems-A systematic literature review

HIFSuite ia a set of tools and application programming interfaces (APIs) that provide support for modeling and verification of HW/SW systems. The core of HIFSuite is the HDL Intermediate Format (HIF) language upon which a set of front-end and back-end tools have been developed to allow the conversion of HDL code into HIF code and vice versa. HIFSuite allows designers to manipulate and integrate heterogeneous components implemented by using different hardware description languages (HDLs). Moreover, HIFSuite includes tools, which rely on HIF APIs, for manipulating HIF descriptions in order to support code abstraction/refinement and postrefinement verification.

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HIFsuite: tools for HDL code conversion and manipulation

Mutation analysis is a widely-adopted strategy in software testing with two main purposes: measuring the quality of test suites, and identifying redundant code in programs. Similar approaches are applied in hardware verification and testing too, especially at RTL or gate level, where mutants are generally referred as faults, and mutation analysis is performed by means of fault modeling and fault simulation. However, in modern embedded systems there is a close integration between HW and SW parts, and verification strategies should be applied early in the design flow. This requires the definition of new mutation analysis-based strategies that work at system level, where HW and SW functionalities are not partitioned yet. In this context, the paper proposes a mutation model for perturbing transaction level modeling (TLM) SystemC descriptions. In particular, the main constructs provided by the SystemC TLM 2.0 library have been analyzed, and a set of mutants is proposed to perturb the primitives related to the TLM communication interfaces.

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A mutation model for the SystemC TLM 2.0 communication interfaces

In recent years, as SoC design research is actively conducted, a large number of IPs are included in one system through network on chip. The real effort and time in using NoC is spent in developing network interfaces (NI) for connecting cores to the NoC. The area and power of NIs should be small and its latency must be kept as low as possible. To reduce power dissipation NIs, we suppose to employ many techniques able to hibernate switchings while no communication is avilable. In this papper, we try to reduce the power dissipation of NoC by reducing the network interface power. We present a hardware design of a low power Network interface design. The low power is obtained by the implementation of a mechanism based on stoppable clock technique for power saving. The stoppable clock technique allows us to shut down each sub module when it is not under running. Experimental results show that adaptability and stoppable clock technique aspects integrated in the proposed NI allow a significant reduction in terms of power while increasing the area.

A low power network interface for network on chip

The demand for IP reuse and system level scalability in System-on-Chip designs is growing. Network-on-chip constitutes a viable solution space to emerging SoC design challenges. In this paper, we present a configurable Network Interface(NI) architecture design approach with smaller area and lower power. The small area is achieved by memory resources sharing in the three modes used by the OCP IP or by many IPs connected to the NI. The low power is obtained by the implementation of a mechanism based on two level of gated clock for power saving. Experimental results show that adaptability, FIFO sharing, and gated clock aspects integrated in the proposed NI allow a significant reduction in terms of area and power.

Network interface sharing for SoCs based NoC

In the systems on chip (SoC) design, the synthesis of communication architecture constitutes the bottleneck which can affect the performances of the system. Various schemes and protocols can be necessary, just as various topologies of interconnection. To reduce the complexity of the communications refinement, we present in this study a model and a synthesis approach for multi-bus communication architecture containing centralized bridge. The automation of the arbiter synthesis step profited from a detailed attention. This stage generates a hierarchical arbiter integrating various priority arbitration modules. The proposed approach was integrated in a toolbox based environment

Communication Architecture Synthesis for Multi-bus SoC

The implementation of a high-performance network-on-chip (NoC) requires an efficient design of the network interface (NI) unit that connects the switched network to the IP cores In this paper, we present a two novel pipelined NI architecture between IPs and router of NOC These network interfaces allow system designers to send data from IPs to NOC, and vice versa with low latency We present how we can apply decoupling between computation and communications to achieve the IP modules and interconnections to be designed independently from each other To validate this approach, we use AMBA AHB IPs standard at the IP side and use the most three used flow control in NoC This NI was modeled in VHDL and implemented on Xilinx Virtex5 FPGA board Experimental results show that the proposed Network Interfaces is feasible and efficient and it is characterized by a good performance criteria's in terms of area, power, speed, latency, and Throughput

Design and implementation of low latency network interface for network on chip

Due to the power limitation and the small size condition of the wireless capsule endoscopy, therefore the principal defiance is to reduce the area and the power consumption. The aim is to preserve acceptable image reconstruction and coding. In this paper, we present a Low complexity and efficient architecture of 1D-DCT based Cordic-Loeffler technique for wireless capsule endoscopy. Our improvement over the original algorithm is performed in CORDIC part. This brings us to reduce the number of addition operations from 18 to 10. As a result, the number of addition is reduced from 38 to 30 operations in the main algorithm. Also, to more ameliorate our results, we used Modified Carry look Ahead adder (MCLA) and Carry Save Adder (CSA) adder which are characterized by low power and high speed compared to classical Carry Look Ahead adder (CLA). Our aim is to provide an optimized architecture in terms of area and power consumption. The proposed design has been implemented on FPGA. Compared to other architectures, the proposed architecture has not only reduced the computation complexity, but also the area and the power consumption. It should be noted that the proposed DCT architecture is very suitable for low-power and high-quality codecs, especially for battery-based systems.

Abdelkrim Zitouni

Papers

A low power network interface for network on chip

Network interface sharing for SoCs based NoC

Communication Architecture Synthesis for Multi-bus SoC

Design and implementation of low latency network interface for network on chip

Low complexity and efficient architecture of 1D-DCT based Cordic-Loeffler for wireless endoscopy capsule