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Art of electronics

From the Publisher:
This work covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concept and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in complexity from simple to research level.

Algorithms for VLSI Physical Design Automation

Recent directions in netlist partitioning: a survey

Many applications in DSP, telecommunications, graphics, and control have computations that either involve a large number of multiplications of one variable with several constants, or can easily be transformed to that form. A proper optimization of this part of the computation, which we call the multiple constant multiplication (MCM) problem, often results in a significant improvement in several key design metrics, such as throughput, area, and power. However, until now little attention has been paid to the MCM problem. After defining the MCM problem, we introduce an effective problem formulation for solving it where first the minimum number of shifts that are needed is computed, and then the number of additions is minimized using common subexpression elimination. The algorithm for common subexpression elimination is based on an iterative pairwise matching heuristic. The power of the MCM approach is augmented by preprocessing the computation structure with a new scaling transformation that reduces the number of shifts and additions. An efficient branch and bound algorithm for applying the scaling transformation has also been developed. The flexibility of the MCM problem formulation enables the application of the iterative pairwise matching algorithm to several other important and common high level synthesis tasks, such as the minimization of the number of operations in constant matrix-vector multiplications, linear transforms, and single and multiple polynomial evaluations. All applications are illustrated by a number of benchmarks.

Multiple constant multiplications: efficient and versatile framework and algorithms for exploring common subexpression elimination

A modulator package (10) with memory mounted adjacent the modulator allowing operation at two different data rates. The first rate is a steady-state data rate that requires a minimal number of wires (16a-d) from processor to array. The second rate is made possible by a memory buffer with different input and output rates and the ability to have a relatively high pin count. The second rate is the burst data rate which is the time it takes the modulator to update for new data.

Monolithic spatial light modulator and memory package

In this article we discuss a test generation, design-for-testability and built-in self-test methodology for two-dimensional iterative logic arrays (ILAs) that perform arithmetic functions. Our approach is unique because a single graph labeling procedure is used to generate test vectors, implement design-for-testability as well as design the circuitry for built-in self-test. The graph labeling is based on mathematical properties of full-addition such as symmetry and self-duality. Circuit modifications are introduced by a systematic procedure based on the graph labeling, that enable them to be tested with a fixed number of tests irrespective of their size. The approach is novel as it also greatly simplifies the processes of on-chip test vector generation and response comparison that are necessary for built-in self-test. Each circuit module is tested in a pseudo-exhaustive manner with deterministic as opposed to random test sequences. This results in a comprehensive test of the circuit for which built-in self-test is designed.

Test generation, design-for-testability and built-in self-test for arithmetic units based on graph labeling

Test generation for arithmetic units by graph labelling.

The problems of circuit partitioning and chip placement have been studied in the past Given a circuit partitioned into chips, one can optimize the placement of the chips on a printed circuit board with regard to a given cost function Conversely, given a placement of the chips on the board, one can optimize the partitioning of the circuit into the chips with regard to the same cost function However, given neither the circuit partitioning nor the chip placement, we are faced with a difficult optimization problem Our target technology is one in which the chips are unpackaged chips placed on a substrate, analogous to the printed circuit board and interconnected together with high density interconnect to realize a complex system We propose a new approach in which the circuit is both partitioned and placed simultaneously by a simulated annealing based algorithm Our approach is seen to yield excellent results in reasonable run times

A new simultaneous circuit partitioning and chip placement approach based on simulated annealing

An auxiliary monolithic integrated circuit chip provides both buffer amplification and testing interfaces. Off-the-shelf monolithic integrated circuit chips can be connected into an electronics system using one of these auxiliary buffer chips before each input port and after each output port, to implement functional testing similar to that done on monolithic integrated circuit chips with built-in test circuitry.

Abhijit Chatterjee

Papers

Test generation, design-for-testability and built-in self-test for arithmetic units based on graph labeling

Test generation for arithmetic units by graph labelling.

A new simultaneous circuit partitioning and chip placement approach based on simulated annealing

Buffer integrated circuit providing testing interface

C-testability for generalized tree structures with applications to wallace trees and other circuits.