This paper evaluates the performance of three operational amplifier (Op-Amp) based instrumentation amplifier (INA) topology using two variants of Op-Amp - one with a very high gain with respect to the other Op-Amp topology. The gain accuracy and common mode rejection ratio (CMRR) of the INA is improved with the use of the very high gain Op-Amp designed using a folded cascode amplifier. The CMRR of the INA using folded cascade Op-Amp is 114 dB which is 43 dB higher to that of INA using differential amplifier.

Improvement of the Gain Accuracy of the Instrumentation Amplifier Using a Very High Gain Operational Amplifier

A high current efficiency two-stage amplifier with inner feedforward path compensation (IFPC) technique is proposed in this paper. To improve the current utilization of the whole structure, the recycling folded cascode amplifier (RFC) is adopted as the first stage, and the inner feedforward path which is used to eliminate the non-dominant pole is composed of the input stage of RFC and the tail current transistor of the second stage amplifier. By using the IFPC technique, the proposed amplifier achieves an extended gain-bandwidth (GBW) and sufficient phase margin (PM) compared to that of the two-stage amplifier using single Miller compensation (SMC). Moreover, this compensation technique avoids extra power consumption since it does not require additional circuits. The proposed two-stage IFPC amplifier was fabricated in a $0.18~\mu \text{m}$ CMOS technology and the chip area of it is about $0.076mm^{2}$ . The simulated open loop AC response shows the DC gain, GBW, and PM are 130dB, 2.01MHz, and 58.3°, respectively. Measured results of transient response show when driving a 120pF load capacitance, the proposed amplifier achieves 368ns average 1% settling time, and about 1.56V/ $\mu \text{s}$ average slew rate (SR). Note that under the condition of 1.8V power supply, the power consumption is only $108\mu W$ , proving the proposed two-stage IFPC amplifier can achieve high current efficiency while maintaining stability.

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A High Current Efficiency Two-Stage Amplifier With Inner Feedforward Path Compensation Technique



Sensing of biomedical signals is crucial for monitoring of various health conditions.
These signals have a very low amplitude (in μV) and a small frequency range (<500 Hz). In
the presence of various common-mode interferences, biomedical signals are difficult to detect. Instrumentation
amplifiers (INAs) are usually preferred to detect these signals due to their high commonmode
rejection ratio (CMRR). Gain accuracy and CMRR are two important parameters associated
with any INA. This article, therefore, focuses on the improvement of the gain accuracy and CMRR of
a low power INA topology.



The objective of this article is to achieve high gain accuracy and CMRR of low power INA
by having high gain operational amplifiers (Op-Amps), which are the building blocks of the INAs.



For the implementation of the Op-Amps and the INAs, the Cadence Virtuoso tool was used.
All the designs and implementation were realized in 0.18 μm CMOS technology.



Three different Op-Amp topologies namely single-stage differential Op-Amp, folded cascode
Op-Amp, and multi-stage Op-Amp were implemented. Using these Op-Amp topologies separately,
three Op-Amp-based INAs were realized and compared. The INA designed using the high gain multistage
Op-Amp topology of low-frequency gain of 123.89 dB achieves a CMRR of 164.1 dB, with the
INA’s gain accuracy as good as 99%, which is the best when compared to the other two INAs realized
using the other two Op-Amp topologies implemented.



 Using very high gain Op-Amps as the building blocks of the INA improves the gain accuracy
of the INA and enhances the CMRR of the INA. The three Op-Amp-based INA designed with
the multi-stage Op-Amps shows state-of-the-art characteristics as its gain accuracy is 99% and CMRR
is as high as 164.1 dB. The power consumed by this INA is 29.25 μW by operating on a power supply
of ±0.9V. This makes this INA highly suitable for low power measurement applications.


Improvement of Gain Accuracy and CMRR of Low Power Instrumentation Amplifier Using High Gain Operational Amplifiers

Trade-offs among power consumption and other design parameters of two-stage recycling folded cascode OTA that using embedded cascode current buffer compensation technology

In this paper, the enhancement of the common- mode rejection ratio (CMRR) of a fully-differential capacitively-coupled chopper instrumentation amplifier (CCIA) used for biomedical signal acquisition system is proposed. To achieve the gain accuracy of the instrumentation amplifier (INA) high gain multi-stage fully-differential operational amplifier (Op-Amp) has been used as the building block. The enhancement of the CMRR is achieved by using common-mode feedback (CMFB) circuit with very high loop gain. The high CMFB loop gain has been achieved by suitable selection of the CMFB circuit and the connection of the CMFB circuit to the multi-stage Op-Amp. The entire circuit has been designed using 180 nm technology with 1.8 V supply. The designed multi-stage Op-Amp has a low-frequency differential mode (A ) and common mode ( ) gain of 123.5 dB and - 105.02 dB, respectively, using a CMFB loop having a gain of 136.3 dB. Using this Op-Amp the designed CCIA achieves a CMRR as high as 145.1 dB with Ad of 40 dB @3dB bandwidth of 10.38 KHz. Finally, the response of the CCIA has been compared with some of the state-of-art designs.

A Novel Technique of Enhancing CMRR of Fully- Differential Instrumentation Amplifier Using High Gain CMFB Loop

A frequency compensation technique for achieving high 3-dB bandwidth in two-stage operational amplifiers is demonstrated in this paper Due to the phenomenon of pole splitting in Miller's Compensation technique in classical op-amp, the 3-dB bandwidth reduces drastically The technique demonstrated in this paper is a modification of Miller's Compensation technique to achieve a significant improvement in the 3-dB bandwidth by introducing an extra stage, consisting of MOS transistors (MOST) The coupling capacitor and a PMOS transistor operating in triode region is connected between the output of the extra stage and the input of the second stage The simulations were carried out in Cadence VIRTUOSO environment using 018 μm CMOS process technology

Abhinav Mishra

Papers

Frequency compensation in two-stage operational amplifiers for achieving high 3-dB bandwidth