The organization of behavior: A neuropsychological theory

An overview of the self-organizing map algorithm, on which the papers in this issue are based, is presented in this article.

The Self-Organizing Map

The scaling of microchip technologies has enabled large scale systems-on-chip (SoC). Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a move from computation-centric to communication-centric design and (ii) the implementation of scalable communication structures. This survey presents a perspective on existing NoC research. We define the following abstractions: system, network adapter, network, and link to explain and structure the fundamental concepts. First, research relating to the actual network design is reviewed. Then system level design and modeling are discussed. We also evaluate performance analysis techniques. The research shows that NoC constitutes a unification of current trends of intrachip communication rather than an explicit new alternative.

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A survey of research and practices of Network-on-chip

We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NOC), includes both the architecture and the design methodology. The NOC architecture is a m/spl times/n mesh of switches and resources are placed on the slots formed by the switches. We assume a direct layout of the 2-D mesh of switches and resources providing physical- and architectural-level design integration. Each switch is connected to one resource and four neighboring switches, and each resource is connected to one switch. A resource can be a processor core, memory, an FPGA, a custom hardware block or any other intellectual property (IP) block, which fits into the available slot and complies with the interface of the NOC. The NOC architecture essentially is the onchip communication infrastructure comprising the physical layer, the data link layer and the network layer of the OSI protocol stack. We define the concept of a region, which occupies an area of any number of resources and switches. This concept allows the NOC to accommodate large resources such as large memory banks, FPGA areas, or special purpose computation resources such as high performance multi-processors. The NOC design methodology consists of two phases. In the first phase a concrete architecture is derived from the general NOC template. The concrete architecture defines the number of switches and shape of the network, the kind and shape of regions and the number and kind of resources. The second phase maps the application onto the concrete architecture to form a concrete product.

A network on chip architecture and design methodology

コンピュータ・サイエンス : ACM computing surveys

Looking into the future, when the billion transitor ASICs will become reality, this p per presents Network on a chip (NOC) concept and its associated methodology as solu the design productivity problem. NOC is a network of computational, storage and I/O resou interconnected by a network of switches. Resources communcate with each other usi dressed data packets routed to their destination by the switch fabric. Arguments are pre to justify that in the billion transistor era, the area and performance penalty would be minim A concrete topology for the NOC, a honeycomb structure, is proposed and discussed. A odology to support NOC is presented. This methodology outlines steps from requirements to implementation. As an illustration of the concepts, a plausible mapping of an entire ba tion on hypothetical NOC is discussed.

Network on Chip : An architecture for billion transistor era

Power consumption in clock of large high performance VLSIs can be reduced by adopting globally asynchronous, locally synchronous design style (GALS) GALS has small overheads for the global asynchronous communication and local clock generation We propose methods to (a) evaluate the benefits of GALS and account for its overheads, which can be used as the basis for partitioning the system into optimal number/size of synchronous blocks, and (b) automate the synthesis of the global asynchronous communication Three realistic ASICs, ranging in complexity from 1 to 3 million gates, were used to evaluate GALS benefits and overheads The results show an average power saving of about 70% in clock with negligible overheads

Lowering power consumption in clock by using globally asynchronous locally synchronous design style

We present a fully automatic approach to hardware/software partitioning and memory allocation by applying compiler techniques to the hardware/software partitioning problem and linking a compiler to a behavioural VHDL generator and high level hardware synthesis tools. Our approach is based on a hierarchical candidate preselection technique and allows (a) efficient collection of profiling data, (b) fast partitioning, and (c) high complexity of the hardware partition.

Hardware/software partitioning and minimizing memory interface traffic

We present an analysis of a fully automatic method to accelerate standard software in C or C++ by use of field programmable gate arrays. Traditional compiler techniques are applied to the hardware/software partitioning problem and a compiler is linked to state of the art hardware synthesis tools. Time critical regions are identified by means of profiling and are automatically implemented in user programmable logic with high level and logic synthesis design tools. The underlying architecture is an add-on board with user programmable logic connected to a Spare based workstation via the system bus. We present an analysis and case study of this method. Eight programs are used as test cases and the data collected by applying this method to programs is used to discuss potentials and limitations of this and similar methods. We discuss architectural parameters, programming language properties, and analysis techniques. >

Ahmed Hemani

Papers

A network on chip architecture and design methodology

Network on Chip : An architecture for billion transistor era

Lowering power consumption in clock by using globally asynchronous locally synchronous design style

Hardware/software partitioning and minimizing memory interface traffic

A case study on hardware/software partitioning