A new fractional-order hyperchaotic memristor oscillator: Dynamic analysis, robust adaptive synchronization, and its application to voice encryption

In the present paper, for the first time, we propose a variable-order hyperchaotic system for information security. Firstly, we study the dynamical behaviors of a memristor oscillator through well-known numerical and analytical tools, such as the Lyapunov exponents, stability of equilibria, and bifurcation diagram. Then as an engineering application, a variable-order fractional version of the system is proposed for sound encryption. In comparison with integer and conventional constant fractional-order chaotic memristor oscillator, the proposed variable-order fractional system shows more complex characteristics and more degrees of freedom due to the existence of time-varying fractional derivatives. Thus, the proposed system is an appropriate choice for data transmission and information security. To illustrate the proper performance of the suggested system for encryption purposes, sound encryption is successfully performed, and its excellent results are demonstrated. The predictor-corrector method is utilized for numerical simulation. Then, a new type-2 fuzzy disturbance observer-based robust control is offered for synchronization of the variable-order hyperchaotic system. The stability and convergence of the disturbance estimator and closed-loop system are proven. Lastly, the synchronization results, which confirm the appropriate performance of the proposed method in the presence of the external disturbances, are demonstrated.

On the variable-order fractional memristor oscillator: Data security applications and synchronization using a type-2 fuzzy disturbance observer-based robust control

In recent days, increasing numbers of Internet and wireless network users have helped accelerate the need for encryption mechanisms and devices to protect user data sharing across an unsecured network. Data security, integrity, and verification may be used due to these features. In internet traffic encryption, symmetrical block chips play an essential role. Data Encryption Standard (DES) and Advanced Encryption Standard (AES) ensure privacy encryption underlying data protection standards. The DES and the AES provide information security. DES and AES have the distinction of being introduced in both hardware and applications. DES and AES hardware implementation has many advantages, such as increased performance and improved safety. This paper provides an exhaustive study of the implementation by DES and AES of field programming gate arrays (FPGAs) using both DES and AES. Since FPGAs can be defined as just one mission, computers are superior to them.

https://journal.qubahan.com/index.php/qaj/article/download/38/22

FPGA Implementations for Data Encryption and Decryption via Concurrent and Parallel Computation: A Review

Nowadays, a huge amount of digital data is frequently changed among different embedded devices over wireless communication technologies. Data security is considered an important parameter for avoiding information loss and preventing cyber-crimes. This research article details the low power high-speed hardware architectures for the efficient field programmable gate array (FPGA) implementation of the advanced encryption standard (AES) algorithm to provide data security. This work does not depend on the Look-Up Table (LUTs) for the implementation the SubBytes and InvSubBytes stages of transformations of the AES encryption and decryption; this new architecture uses combinational logical circuits for implementing SubBytes and InvSubBytes transformation. Due to the elimination of LUTs, unwanted delays are eliminated in this architecture and a subpipelining structure is introduced for improving the speed of the AES algorithm. Here, modified positive polarity reed muller (MPPRM) architecture is inserted to reduce the total hardware requirements, and comparisons are made with different implementations. With MPPRM architecture introduced in SubBytes stages, an efficient mixcolumn and invmixcolumn architecture that is suited to subpipelined round units is added. The performances of the proposed AES-MPPRM architecture is analyzed in terms of number of slice registers, flip flops, number of slice LUTs, number of logical elements, slices, bonded IOB, operating frequency and delay. There are five different AES architectures including LAES, AES-CTR, AES-CFA, AES-BSRD, and AES-EMCBE. The LUT of the AES-MPPRM architecture designed in the Spartan 6 is reduced up to 15.45% when compared to the AES-BSRD.

/pdf/a-low-area-high-speed-fpga-implementation-of-aes-25ytl4w9vd.pdf

A Low Area High Speed FPGA Implementation of AES Architecture for Cryptography Application

This paper proposes a new fractional-order multi-scrolls chaotic system. More complex systems and flexible ranges of the chaotic behavior are obtained due to the extra parameters added by the fractional-order. The proposed system has novel complex chaotic behaviors. The effect of changing the system parameters on the system behavior is investigated and their bifurcation diagrams have been provided. The MLE for the proposed system in integer and fractional domain has been discussed. It shows that the proposed chaotic system is richer in the case of fractional-order. A novel FPGA design automation tool for the proposed system is also proposed. It provides an optimized FPGA implementation of the system according to different system parameters. Additionally, it provides a facility and fast way to accelerate the design process for the developer to design their own module while applying the system in different applications. The proposed tool has been tested using Xilinx's Virtex-5 XC5VLX50T FPGA and verified using MATLAB. The experimental results are provided for different design peripherals options. Finally, a procedure to generalize the proposed tool to involve any other chaotic system is presented.

Fractional X-shape controllable multi-scroll attractor with parameter effect and FPGA automatic design tool software

FPGA implementation of sound encryption system based on fractional-order chaotic systems

This paper introduces FPGA implementation of fractional order double scrolls chaotic system based on Chua circuit. Grunwald-Letnikov's (GL) definition is used to generalize the chaotic system equations into the fractional-order domain. Xilinx ISE 14.5 is used to simulate the proposed design and Artix-7 XC7A100T FPGA is used for system realization. Experimental results are presented on digital oscilloscope and the error between theoretical and experimental results is calculated. Also, various interesting attractors are obtained with respect to different parameters values and window sizes. Some techniques have been employed to increase the throughput to 7.685 Gbit/Sec with 96-bits overall output.

FPGA implementation of fractional-order Chua's chaotic system

Convolutional neural networks (CNNs) have dominated image recognition and object detection models in the last few years. They can achieve the highest accuracies with several applications such as automotive and biomedical applications. CNNs are usually implemented by using Graphical Processing Units (GPUs) or generic processors. Although the GPUs are capable of performing the complex computations needed by the CNNs, their power consumption is huge compared to generic processors. Moreover, current generic processors are unable to cope up with the growing CNNs demand for computation performance. Therefore, hardware accelerators are the best choice to provide the required computation performance needed by the CNNs as well as affordable power consumption. Several techniques are adopted in hardware accelerators such as pruning and quantization. In this paper, a low-power dedicated CNN hardware accelerator is proposed based on GoogLeNet CNN as a case study. Weights pruning and quantization are applied to reduce the memory size by $57.6\times $ . Consequently, only FPGA on-chip memory is used for weights and activations storage without using offline DRAMs (Dynamic Random Access Memories). In addition, the proposed hardware accelerator utilizes zero DSP (Digital Signal Processing) units as all multiplications are replaced by shifting operations. The accelerator is developed based on a time-sharing/pipelined architecture, which processes the CNN model layer by layer. The architecture proposes a new data fetching mechanism that increases data reuse. Moreover, the proposed accelerator units are implemented in native RTL (Register Transfer Logic). The accelerator classifies 25.1 frames per second (fps) with 3.92W only, which is more power-efficient than other GoogLeNet implementations on FPGA in the literature. In addition, the proposed accelerator achieves an average classification efficiency of 91%, which is significantly higher than comparable architectures. Furthermore, this accelerator surpasses the popular CPUs such as Intel Core-i7 and GPUs such as GTX 1080Ti in terms of the number of frames processed per Watt.

Power Efficient Design of High-Performance Convolutional Neural Networks Hardware Accelerator on FPGA: A Case Study With GoogLeNet

This paper introduces the hardware and the ASIC implementations of the four most popular biologically inspired neuron models. The models are quartic, Izhikevich, Hindmarsh Rose and Fitzhugh-Nagumo. Moreover, some approximate computing techniques are applied on these models to reduce the area and power consumption. In addition, ASIC implementations of these models and their approximate versions are carried out. Also, spiking behavior error between these models and the Hodgkin Huxley model, the reference accurate model, is presented. Finally, a fair comparative analysis is discussed to help the Spiking Neural Networks designers to select the best neuron model hardware implementation from the power, area and accuracy perspectives.

ASIC Oriented Comparative Analysis Of Biologically Inspired Neuron Models

Chaotic systems have remarkable importance in capturing some complex features of the physical process. Recently, fractional calculus becomes a vigorous tool in characterizing the dynamics of complex systems. The fractional-order chaotic systems increase the chaotic behavior in new dimensions and add extra degrees of freedom, which increase system controllability. In this chapter, FPGA implementation of different integer and fractional-order chaotic systems is presented. The investigated integer-order systems include Chua double scroll chaotic system and the modified Chua N-scroll chaotic system. The investigated fractional-order systems include Chua, Yalcin et al., Ozuogos et al., and Tang et al., chaotic systems. These systems are implemented and simulated based on the Grunwald–Letnikov (GL) definition with different window sizes. The parameters effect, along with different GL window sizes is investigated where some interesting chaotic behaviors are obtained. The proposed FPGA implementation utilizes fewer resources and has high throughput. Experimental results are provided on a digital oscilloscope.

Ahmed J. Abd El-Maksoud

Papers

FPGA implementation of sound encryption system based on fractional-order chaotic systems

FPGA implementation of fractional-order Chua's chaotic system

Power Efficient Design of High-Performance Convolutional Neural Networks Hardware Accelerator on FPGA: A Case Study With GoogLeNet

ASIC Oriented Comparative Analysis Of Biologically Inspired Neuron Models

FPGA Implementation of Integer/Fractional Chaotic Systems