Underlying physical mechanisms controlling the noise properties of oscillators are studied. This treatment shows the importance of inductance selection for oscillator noise optimization. A design strategy centered around an inductance selection scheme is executed using a practical graphical optimization method to optimize phase noise subject to design constraints such as power dissipation, tank amplitude, tuning range, startup condition, and diameters of spiral inductors. The optimization technique is demonstrated through a design example, leading to a 2.4-GHz fully integrated, LC voltage-controlled oscillator (VCO) implemented using 0.35-/spl mu/m MOS transistors. The measured phase-noise values are -121, -117, and -115 dBc/Hz at 600-kHz offset from 1.91, 2.03, and 2.60-GHz carriers, respectively. The VCO dissipates 4 mA from a 2.5-V supply voltage. The inversion mode MOSCAP tuning is used to achieve 26% of tuning range. Two figures of merit for performance comparison of various oscillators are introduced and used to compare this work to previously reported results.

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Concepts and methods in optimization of integrated LC VCOs

A completely integrated 1.8-GHz low-phase-noise voltage-controlled oscillator (VCO) has been realized in a standard silicon digital CMOS process. The design relies heavily on the integrated spiral inductors which have been realized with only two metal layers and without etching. The effects of high-frequency magnetic fields and losses in the heavily doped substrate have been simulated and modeled with finite-element analysis. The achieved phase noise is as low as -116 dBc/Hz at an offset frequency of 600 kHz, at a power consumption of only 6 mW. The VCO is tuned with standard available junction capacitances, resulting in a 250-MHz tuning range.

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A 1.8-GHz low-phase-noise CMOS VCO using optimized hollow spiral inductors

Practical considerations in the design of CMOS charge pumps are discussed. The non-ideal effects of the charge pump due to the leakage current, the mismatch, and the delay offset in the P/FD are quantitatively analyzed. To use the appropriate charge pump in various PLL applications, several architectures are investigated and their performances are compared. The improved design of both the single-ended and the differential charge pumps are presented with the simulation result.

Design of high-performance CMOS charge pumps in phase-locked loops

A general model of phase-locked loops (PLLs) is derived which incorporates the influence of divide value variations. The proposed model allows straightforward noise and dynamic analyses of /spl Sigma/-/spl Delta/ fractional-N frequency synthesizers and other PLL applications in which the divide value is varied in time. Based on the derived model, a general parameterization is presented that further simplifies noise calculations. The framework is used to analyze the noise performance of a custom /spl Sigma/-/spl Delta/ synthesizer implemented in a 0.6 /spl mu/m CMOS process, and accurately predicts the measured phase noise to within 3 dB over the entire frequency offset range spanning 25 kHz to 10 MHz.

/pdf/a-modeling-approach-for-spl-sigma-spl-delta-fractional-n-11dhjv5aj5.pdf

A modeling approach for /spl Sigma/-/spl Delta/ fractional-N frequency synthesizers allowing straightforward noise analysis

A prototype frequency synthesizer for the DCS-1800 system has been integrated in a standard 0.4 /spl mu/m CMOS process without any external components. A completely monolithic design has been made feasible by using an optimized hollow-coil inductor low-phase-noise voltage-controlled oscillator (VCO). The frequency divider is an eight-modulus phase-switching prescaler that achieves the same speed as asynchronous dividers. The die area was minimized by using a dual-path active loop filter. An indirect linearization technique was implemented for the VCO gain. The resulting architecture is a fourth-order, type-2 charge-pump phase-locked loop. The measured settling time is 300 /spl mu/s, and the phase noise is up to -123 dBc/Hz at 600 kHz and -138 dBc/Hz at 3 MHz offset.

A fully integrated CMOS DCS-1800 frequency synthesizer

Fractional-N frequency synthesis based on /spl Delta//spl Sigma/ modulators offers wide bandwidth with narrow channel spacing and alleviates PLL design constraints for phase noise and reference spur. However, the synthesizer phase noise performance is significantly affected by the high-frequency out-of-band noise, which is difficult to suppress with the finite number of PLL loop filter poles. This work uses a 3b 3rd-order modulator that generates less high-frequency noise and makes the system less sensitive to the phase detector nonlinearity.

A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order /spl Delta//spl Sigma/ modulator

A 1.1 GHz CMOS fractional-N frequency synthesizer with a 3b 3rd-order ΔΣ modulator

A gated-delay locked loop that generates an output clock in phase with and having a frequency which is an integer multiple of the frequency of a reference clock. The gated delay-locked loop includes a voltage-controlled gated oscillator having first and second serially connected voltage-controlled delay elements that each introduce a time delay to produce a first delayed clock and the output clock. An S-R flip-flop receives the first delayed clock on its R-input and either the output clock or the reference clock on its S-input to produce a loop clock. The loop clock is provided to the first delay element. A multiplexer selects the reference clock as the S input to the flip-flop once every N cycles, and selects the output clock as the S input the remaining N−1 cycles. A phase detector, a charge pump and a loop filter compare the phase of the output clock to the phase of the reference clock and apply a voltage to the delay elements to correct any phase differences.

Gated delay-locked loop for clock generation applications

A phase locked loop (PLL) circuit with time-delayed phase/frequency detector (PFD) input signals and a method for generating high PFD gain in such a circuit is provided. One circuit embodiment includes a first divider, a phase/frequency detector having a plurality of input pairs, a plurality of input signal reference delay elements connected in a series between the first divider and the PFD, a charge pump, a loop filter, a voltage-controlled oscillator (VCO), a second divider, and a plurality of feedback signal delay elements connected in a series. The corresponding method embodiment includes steps for receiving digital input signals with reference frequency and period T in the first divider, dividing the reference frequency by a value R, providing a plurality of time-delayed PFD reference input signals in each period T, dividing the VCO frequency by a value M in the second divider, and providing a plurality of time-delayed PFD feedback input signals in each period T. The delayed reference signal and the delayed feedback signal at each PFD input pair have the same time delay. Another embodiment circuit has a first divider, a plurality of phase/frequency detectors (PFDs), a charge pump, two OR gates, a loop filter, a voltage-controlled oscillator (VCO), and a second divider. The corresponding method embodiment includes the steps for receiving reference frequency signals in the first divider, dividing the reference frequency by a value R, and creating a plurality of time-delayed reference output signals in each period T for PFD reference inputs, or-ing the output signals from the plurality of the PDFs to supply the charge pump, dividing the VCO frequency by a value M in the second divider, creating a plurality of time-delayed feedback output signals in each period T, and supplying each PFD feedback input with one of the plurality of time-delayed feedback output signals.

Phase/frequency detector with time-delayed inputs in a charge pump based phase locked loop and a method for enhancing the phase locked loop gain

Integration of general-purpose frequency synthesizers usually requires a BiCMOS process and necessitates a compromise between the level of integration and performance. Frequency synthesizers with extensive channel programming flexibility and low phase noise typically require external voltage-controlled oscillators (VCOs) while highly-integrated synthesizers utilizing on-chip VCOs tend to exhibit degraded phase-noise performance. The frequency synthesizer presented here features low reference spurs and low phase-noise and is fully-integrated with the exception of an external crystal and an RC loop-filter. It uses a 25 GHz f/sub /spl tau// silicon bipolar process and is for 900 MHz ISM band applications and operates over a supply voltage range of 2.7 V to 5.0 V. The integration level is achieved by a simplified pulse-swallow architecture that provides 41 channels with a 600 kHz spacing and requires a 6 bit programming word.

Akbar Ali

Papers

A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order /spl Delta//spl Sigma/ modulator

A 1.1 GHz CMOS fractional-N frequency synthesizer with a 3b 3rd-order ΔΣ modulator

Gated delay-locked loop for clock generation applications

Phase/frequency detector with time-delayed inputs in a charge pump based phase locked loop and a method for enhancing the phase locked loop gain

A 900 MHz frequency synthesizer with integrated LC voltage-controlled oscillator