An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.

Nonvolatile Semiconductor Memory Device

A semiconductor memory device comprising; (A) a transistor, (B) a capacitor member formed above said transistor through an insulating interlayer, said capacitor member comprising a lower electrode, a capacitor layer formed of a high-dielectric-constant material or a ferroelectric material and an upper electrode, (C) a contact plug formed in said insulating interlayer, for electrically connecting the lower electrode formed on the insulating interlayer with the transistor, and (D) a diffusion barrier layer formed between the lower electrode and the contact plug, said semiconductor memory device further comprising (E) an adhesion layer formed at least between the lower electrode and the diffusion barrier layer, and said adhesion layer consisting of an alloy that contains a noble metal element as a main component, and contains, as a component, a metal element that differs from any one of the noble metal element, an alkali element and an alkaline earth metal element and that contains no oxygen atom.

Semiconductor memory device

In accordance with a preferred embodiment of the present invention, a silicon-on-insulator (SOI) chip includes a silicon layer of a predetermined thickness overlying an insulator layer. A multiple-gate fully-depleted SOI MOSFET including a strained channel region is formed on a first portion of the silicon layer. A planar SOI MOSFET including a strained channel region formed on another portion of the silicon layer. For example, the planar SOI MOSFET can be a planar fully-depleted SOI (FD-SOI) MOSFET or the planar SOI MOSFET can be a planar partially-depleted SOI (PD-SOI) MOSFET.

Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors

A semiconductor chip includes a semiconductor substrate 126, in which first and second active regions are disposed. A resistor 124 is formed in the first active region and the resistor 124 includes a doped region 128 formed between two terminals 136. A strained channel transistor 132 is formed in the second active region. The transistor includes a first and second stressor 141, formed in the substrate oppositely adjacent a strained channel region 143.

Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit

In a sea-of-gate structure gate array in which a plurality of logic gates are arrayed on a semiconductor chip, resistance devices or capacitive devices are formed without reducing the gate scale to form analog components to render the gate array into a hybrid gate array including the analog components. A number of MOS transistors to be formed without vacancies on the chip surface are formed in a thin silicon section on an insulating layer 15. The logic gates arrayed on the chip is of the SOI structure. Below the insulating layer 15, a lower capacitor electrode 12, a dielectric film 13, an upper capacitor electrode 14 and a resistance element are formed so as to be buried in an insulating film 11 on a supporting substrate 10 or in an insulating substrate. The capacitor and the resistance are led to the chip surface by means of a contact hole 23 provided in the insulating layer 15. A grinding stop 16 is formed in the insulating layer 15. The thin silicon section of the SOI structure is produced by grinding the substrate.

Semiconductor integrated circuit device with plural gates and plural passive devices

A capacitor structure of a semiconductor memory cell, comprises: a lower electrode formed on an insulation layer; a capacitor insulation film in form of a ferroelectric thin film formed on the lower electrode; and an upper electrode formed on the capacitor insulation layer, the lower electrode including a column-shaped projection made of a conductive material formed on the insulation layer, and a lower electrode layer covering the projection, and the ferroelectric thin film being formed on the lower electrode layer as originally stacked. A method for fabricating a capacitor structure of a semiconductor memory cell, comprises the steps of: forming a conductive material layer on an insulation layer, then patterning the conductive material layer to form a column-shaped projection of a conductive material on the insulation layer; stacking a lower electrode layer on the insulation layer including the surface of the column-shaped projection; stacking a ferroelectric thin film on the lower electrode layer as originally stacked; stacking an upper electrode layer on the ferroelectric thin film; and patterning the lower electrode layer, the ferroelectric thin film and the lower electrode layer to form a capacitor structure including a lower electrode, a capacitor insulation film in form of the ferroelectric thin film, and an upper electrode.

Semiconductor memory cell using a ferroelectric thin film and a method for fabricating it

Provided is a semiconductor memory device in which defective contact, deterioration in transistor characteristics and other problems are solved with a thermally stable, conductive diffusion barrier layer against oxygen, and against constituent elements in a plug material and a lower electrode, formed at the interface between a plug and the lower electrode made of a noble metal. The semiconductor memory device comprises a dielectric capacitor of a stacked structure including a first electrode (a lower electrode), a dielectric film and a second electrode (an upper electrode) and a conductive plug connected to the lower electrode, wherein the lower electrode connected to the conductive plug includes a metal suboxide layer with conductiveness and a diffusion barrier layer blocking diffusion of oxygen, and the metal suboxide layer and the diffusion barrier layer are stacked in the order from the conductive plug side of the lower electrode.

Oxygen diffusion blocking semiconductor capacitor

A capacitor in a ferroelectric nonvolatile memory (FERAM) comprising a lower electrode formed on a semiconductor substrate; a ferroelectric thin film formed on the lower electrode; an upper electrode formed on the ferroelectric thin film; a first protective layer consisting of one or more layers formed between the semiconductor substrate and the lower electrode, and composed of a material selected from those of Group IVa transition metal, Group Va transition metal, Group IVa transition metal nitride, Group Va transition metal nitride, silicon nitride, nickel and palladium; and a second protective layer consisting of one or more layers formed on the upper electrode, and composed of a material selected from those of Group IVa transition metal, Group Va transition metal, Group IVa transition metal nitride, Group Va transition metal nitride, nickel and palladium. Since the ferroelectric capacitor is enclosed with composite films of such materials, it becomes possible to prevent diffusion of hydrogen and intrusion of water content therein to consequently avert deterioration of the characteristics.

Method of manufacturing capacitor having ferroelectric film for nonvolatile memory cell

PROBLEM TO BE SOLVED: To suppress the intrusion of hydrogen and moisture into a capacitor structure, and to enhance long-term reliability by a method wherein the capacitor structure of a semiconductor memory element is surrounded by the first and the second protective layers consisting of the material such as a 4A group and a 5A transition metal etc. SOLUTION: A capacitor structure is formed on the interlayer insulating film 20 located on the element isolation region 11. Said capacitor structure is composed of a lower electrode 22, a capacitor part 23 consisting of ferroelectric thin film, and an upper electrode 26. Said lower electrode 22 is formed on the interlayer insulating layer 20 corresponding to a substrate. The first protective layer 21 is formed between the interlayer insulating layer 20 and the lower electrode 22. On the other hand, the second protective layer 27 is formed on the upper electrode 26. The first protective layer 21 and the second protective layer 27 have the two-layer structure composed of a 4A group transition metal (Ti) layer and a 4A group transition metal nitride (TiN) layer. Said Ti layer is the lower layer and the TiN layer is the upper layer.

Akihiko Ochiai

Papers

Semiconductor integrated circuit device with plural gates and plural passive devices

Semiconductor memory cell using a ferroelectric thin film and a method for fabricating it

Oxygen diffusion blocking semiconductor capacitor

Method of manufacturing capacitor having ferroelectric film for nonvolatile memory cell

Capacitor structure of semiconductor memory element and manufacture thereof